2019-04-29 21:25:05 +00:00
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// Copyright 2018 The gVisor Authors.
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2018-04-27 17:37:02 +00:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef VDSO_CYCLE_CLOCK_H_
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#define VDSO_CYCLE_CLOCK_H_
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#include <stdint.h>
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#include "vdso/barrier.h"
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namespace vdso {
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#if __x86_64__
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2019-04-29 21:03:04 +00:00
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// TODO(b/74613497): The appropriate barrier instruction to use with rdtsc on
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2018-04-27 17:37:02 +00:00
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// x86_64 depends on the vendor. Intel processors can use lfence but AMD may
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// need mfence, depending on MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT.
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static inline uint64_t cycle_clock(void) {
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uint32_t lo, hi;
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asm volatile("lfence" : : : "memory");
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asm volatile("rdtsc" : "=a"(lo), "=d"(hi));
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return ((uint64_t)hi << 32) | lo;
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}
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2019-04-18 23:20:45 +00:00
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#elif __aarch64__
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static inline uint64_t cycle_clock(void) {
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uint64_t val;
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asm volatile("mrs %0, CNTVCT_EL0" : "=r"(val)::"memory");
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return val;
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}
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2018-04-27 17:37:02 +00:00
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#else
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#error "unsupported architecture"
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#endif
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} // namespace vdso
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#endif // VDSO_CYCLE_CLOCK_H_
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