Merge pull request #3605 from lubinszARM:pr_helloworld_thunderx2
PiperOrigin-RevId: 326326710
This commit is contained in:
commit
252329c1f3
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@ -101,6 +101,8 @@ func NewFloatingPointData() *FloatingPointData {
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// State contains the common architecture bits for aarch64 (the build tag of this
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// file ensures it's only built on aarch64).
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//
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// +stateify savable
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type State struct {
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// The system registers.
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Regs Registers
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@ -73,6 +73,8 @@ const (
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)
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// context64 represents an ARM64 context.
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//
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// +stateify savable
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type context64 struct {
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State
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sigFPState []aarch64FPState // fpstate to be restored on sigreturn.
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@ -72,6 +72,7 @@ const (
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_TCR_T0SZ_VA48 = 64 - 48 // VA=48
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_TCR_T1SZ_VA48 = 64 - 48 // VA=48
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_TCR_A1 = 1 << 22
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_TCR_ASID16 = 1 << 36
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_TCR_TBI0 = 1 << 37
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@ -61,7 +61,6 @@ func (c *vCPU) initArchState() error {
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reg.addr = uint64(reflect.ValueOf(&data).Pointer())
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regGet.addr = uint64(reflect.ValueOf(&dataGet).Pointer())
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vcpuInit.target = _KVM_ARM_TARGET_GENERIC_V8
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vcpuInit.features[0] |= (1 << _KVM_ARM_VCPU_PSCI_0_2)
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if _, _, errno := syscall.RawSyscall(
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syscall.SYS_IOCTL,
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@ -272,8 +271,16 @@ func (c *vCPU) SwitchToUser(switchOpts ring0.SwitchOpts, info *arch.SignalInfo)
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return c.fault(int32(syscall.SIGSEGV), info)
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case ring0.Vector(bounce): // ring0.VirtualizationException
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return usermem.NoAccess, platform.ErrContextInterrupt
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case ring0.El0Sync_undef,
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ring0.El1Sync_undef:
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*info = arch.SignalInfo{
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Signo: int32(syscall.SIGILL),
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Code: 1, // ILL_ILLOPC (illegal opcode).
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}
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info.SetAddr(switchOpts.Registers.Pc) // Include address.
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return usermem.AccessType{}, platform.ErrContextSignal
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default:
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return usermem.NoAccess, platform.ErrContextSignal
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panic(fmt.Sprintf("unexpected vector: 0x%x", vector))
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}
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}
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@ -364,6 +364,9 @@ TEXT ·Halt(SB),NOSPLIT,$0
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CMP RSV_REG, R9
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BNE mmio_exit
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MOVD $0, CPU_REGISTERS+PTRACE_R9(RSV_REG)
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// Flush dcache.
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WORD $0xd5087e52 // DC CISW
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mmio_exit:
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// Disable fpsimd.
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WORD $0xd5381041 // MRS CPACR_EL1, R1
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@ -381,6 +384,9 @@ mmio_exit:
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MRS VBAR_EL1, R9
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MOVD R0, 0x0(R9)
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// Flush dcahce.
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WORD $0xd5087e52 // DC CISW
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RET
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// HaltAndResume halts execution and point the pointer to the resume function.
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@ -414,6 +420,7 @@ TEXT ·Current(SB),NOSPLIT,$0-8
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// Prepare the vcpu environment for container application.
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TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
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// Step1, save sentry context into memory.
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MRS TPIDR_EL1, RSV_REG
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REGISTERS_SAVE(RSV_REG, CPU_REGISTERS)
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MOVD RSV_REG_APP, CPU_REGISTERS+PTRACE_R9(RSV_REG)
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@ -425,34 +432,13 @@ TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
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MOVD CPU_REGISTERS+PTRACE_R3(RSV_REG), R3
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// Step2, save SP_EL1, PSTATE into kernel temporary stack.
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// switch to temporary stack.
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// Step2, switch to temporary stack.
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LOAD_KERNEL_STACK(RSV_REG)
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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SUB $STACK_FRAME_SIZE, RSP, RSP
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MOVD CPU_REGISTERS+PTRACE_SP(RSV_REG), R11
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MOVD CPU_REGISTERS+PTRACE_PSTATE(RSV_REG), R12
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STP (R11, R12), 16*0(RSP)
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MOVD CPU_REGISTERS+PTRACE_R11(RSV_REG), R11
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MOVD CPU_REGISTERS+PTRACE_R12(RSV_REG), R12
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// Step3, test user pagetable.
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// If user pagetable is empty, trapped in el1_ia.
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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SWITCH_TO_APP_PAGETABLE(RSV_REG)
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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SWITCH_TO_KVM_PAGETABLE(RSV_REG)
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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// If pagetable is not empty, recovery kernel temporary stack.
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ADD $STACK_FRAME_SIZE, RSP, RSP
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// Step4, load app context pointer.
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// Step3, load app context pointer.
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MOVD CPU_APP_ADDR(RSV_REG), RSV_REG_APP
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// Step5, prepare the environment for container application.
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// Step4, prepare the environment for container application.
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// set sp_el0.
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MOVD PTRACE_SP(RSV_REG_APP), R1
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WORD $0xd5184101 //MSR R1, SP_EL0
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@ -480,13 +466,13 @@ TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
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LDP 16*0(RSP), (RSV_REG, RSV_REG_APP)
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ADD $STACK_FRAME_SIZE, RSP, RSP
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ISB $15
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ERET()
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// kernelExitToEl1 is the entrypoint for sentry in guest_el1.
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// Prepare the vcpu environment for sentry.
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TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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MOVD CPU_REGISTERS+PTRACE_PSTATE(RSV_REG), R1
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WORD $0xd5184001 //MSR R1, SPSR_EL1
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@ -503,6 +489,8 @@ TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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// Start is the CPU entrypoint.
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TEXT ·Start(SB),NOSPLIT,$0
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// Flush dcache.
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WORD $0xd5087e52 // DC CISW
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// Init.
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MOVD $SCTLR_EL1_DEFAULT, R1
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MSR R1, SCTLR_EL1
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@ -558,6 +546,7 @@ TEXT ·El1_sync(SB),NOSPLIT,$0
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B el1_invalid
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el1_da:
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el1_ia:
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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WORD $0xd538601a //MRS FAR_EL1, R26
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@ -570,9 +559,6 @@ el1_da:
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B ·HaltAndResume(SB)
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el1_ia:
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B ·HaltAndResume(SB)
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el1_sp_pc:
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B ·Shutdown(SB)
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@ -644,9 +630,10 @@ el0_svc:
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MOVD $Syscall, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·HaltAndResume(SB)
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B ·kernelExitToEl1(SB)
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el0_da:
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el0_ia:
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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WORD $0xd538601a //MRS FAR_EL1, R26
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@ -658,10 +645,10 @@ el0_da:
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MOVD $PageFault, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·HaltAndResume(SB)
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MRS ESR_EL1, R3
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MOVD R3, CPU_ERROR_CODE(RSV_REG)
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el0_ia:
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B ·Shutdown(SB)
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B ·kernelExitToEl1(SB)
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el0_fpsimd_acc:
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B ·Shutdown(SB)
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@ -676,7 +663,10 @@ el0_sp_pc:
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B ·Shutdown(SB)
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el0_undef:
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B ·Shutdown(SB)
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MOVD $El0Sync_undef, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·kernelExitToEl1(SB)
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el0_dbg:
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B ·Shutdown(SB)
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@ -53,7 +53,6 @@ func IsCanonical(addr uint64) bool {
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//go:nosplit
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func (c *CPU) SwitchToUser(switchOpts SwitchOpts) (vector Vector) {
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// Sanitize registers.
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regs := switchOpts.Registers
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regs.Pstate &= ^uint64(PsrFlagsClear)
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@ -69,6 +68,5 @@ func (c *CPU) SwitchToUser(switchOpts SwitchOpts) (vector Vector) {
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vector = c.vecCode
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// Perform the switch.
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return
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}
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@ -72,13 +72,14 @@ const (
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)
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const (
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mtNormal = 0x4 << 2
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mtDevicenGnRE = 0x1 << 2
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mtNormal = 0x4 << 2
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)
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const (
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executeDisable = xn
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optionMask = 0xfff | 0xfff<<48
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protDefault = accessed | shared | mtNormal
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protDefault = accessed | shared
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)
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// MapOpts are x86 options.
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@ -184,8 +185,10 @@ func (p *PTE) Set(addr uintptr, opts MapOpts) {
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if opts.User {
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v |= user
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v |= mtNormal
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} else {
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v = v &^ user
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v |= mtDevicenGnRE // Strong order for the addresses with ring0.KernelStartAddress.
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}
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atomic.StoreUintptr((*uintptr)(p), v)
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}
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@ -200,7 +203,7 @@ func (p *PTE) setPageTable(pt *PageTables, ptes *PTEs) {
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// This should never happen.
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panic("unaligned physical address!")
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}
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v := addr | typeTable | protDefault
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v := addr | typeTable | protDefault | mtNormal
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atomic.StoreUintptr((*uintptr)(p), v)
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}
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