Merge pull request #1271 from lubinszARM:pr_ring0_1
PiperOrigin-RevId: 297230721
This commit is contained in:
gVisor bot
commit
813b1b0486
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@ -25,10 +25,14 @@
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// not available for calls.
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//
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// ERET returns using the ELR and SPSR for the current exception level.
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#define ERET() \
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WORD $0xd69f03e0
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// RSV_REG is a register that holds el1 information temporarily.
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#define RSV_REG R18_PLATFORM
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// RSV_REG_APP is a register that holds el0 information temporarily.
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#define RSV_REG_APP R9
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#define FPEN_NOTRAP 0x3
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@ -36,6 +40,12 @@
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#define FPEN_ENABLE (FPEN_NOTRAP << FPEN_SHIFT)
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// Saves a register set.
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//
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// This is a macro because it may need to executed in contents where a stack is
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// not available for calls.
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//
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// The following registers are not saved: R9, R18.
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#define REGISTERS_SAVE(reg, offset) \
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MOVD R0, offset+PTRACE_R0(reg); \
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MOVD R1, offset+PTRACE_R1(reg); \
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@ -67,6 +77,12 @@
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MOVD R29, offset+PTRACE_R29(reg); \
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MOVD R30, offset+PTRACE_R30(reg);
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// Loads a register set.
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//
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// This is a macro because it may need to executed in contents where a stack is
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// not available for calls.
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//
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// The following registers are not loaded: R9, R18.
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#define REGISTERS_LOAD(reg, offset) \
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MOVD offset+PTRACE_R0(reg), R0; \
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MOVD offset+PTRACE_R1(reg), R1; \
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@ -98,7 +114,7 @@
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MOVD offset+PTRACE_R29(reg), R29; \
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MOVD offset+PTRACE_R30(reg), R30;
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//NOP
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// NOP-s
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#define nop31Instructions() \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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@ -254,6 +270,7 @@
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#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
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#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
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// LOAD_KERNEL_ADDRESS loads a kernel address.
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#define LOAD_KERNEL_ADDRESS(from, to) \
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MOVD from, to; \
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ORR $0xffff000000000000, to, to;
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@ -263,15 +280,18 @@
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LOAD_KERNEL_ADDRESS(CPU_SELF(from), RSV_REG); \
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MOVD $CPU_STACK_TOP(RSV_REG), RSV_REG; \
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MOVD RSV_REG, RSP; \
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WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
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ISB $15; \
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DSB $15;
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// SWITCH_TO_APP_PAGETABLE sets a new pagetable for a container application.
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#define SWITCH_TO_APP_PAGETABLE(from) \
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MOVD CPU_TTBR0_APP(from), RSV_REG; \
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WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
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ISB $15; \
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DSB $15;
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// SWITCH_TO_KVM_PAGETABLE sets the kvm pagetable.
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#define SWITCH_TO_KVM_PAGETABLE(from) \
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MOVD CPU_TTBR0_KVM(from), RSV_REG; \
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WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
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@ -294,6 +314,7 @@
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WORD $0xd5181040; \ //MSR R0, CPACR_EL1
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ISB $15;
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// KERNEL_ENTRY_FROM_EL0 is the entry code of the vcpu from el0 to el1.
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#define KERNEL_ENTRY_FROM_EL0 \
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SUB $16, RSP, RSP; \ // step1, save r18, r9 into kernel temporary stack.
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STP (RSV_REG, RSV_REG_APP), 16*0(RSP); \
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@ -315,19 +336,22 @@
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WORD $0xd5384103; \ // MRS SP_EL0, R3
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MOVD R3, PTRACE_SP(RSV_REG_APP);
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// KERNEL_ENTRY_FROM_EL1 is the entry code of the vcpu from el1 to el1.
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#define KERNEL_ENTRY_FROM_EL1 \
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WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
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REGISTERS_SAVE(RSV_REG, CPU_REGISTERS); \ // save sentry context
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REGISTERS_SAVE(RSV_REG, CPU_REGISTERS); \ // Save sentry context.
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MOVD RSV_REG_APP, CPU_REGISTERS+PTRACE_R9(RSV_REG); \
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WORD $0xd5384004; \ // MRS SPSR_EL1, R4
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MOVD R4, CPU_REGISTERS+PTRACE_PSTATE(RSV_REG); \
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MRS ELR_EL1, R4; \
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MOVD R4, CPU_REGISTERS+PTRACE_PC(RSV_REG); \
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MOVD RSP, R4; \
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MOVD R4, CPU_REGISTERS+PTRACE_SP(RSV_REG);
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MOVD R4, CPU_REGISTERS+PTRACE_SP(RSV_REG); \
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LOAD_KERNEL_STACK(RSV_REG); // Load the temporary stack.
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// Halt halts execution.
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TEXT ·Halt(SB),NOSPLIT,$0
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// clear bluepill.
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// Clear bluepill.
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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CMP RSV_REG, R9
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BNE mmio_exit
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@ -341,8 +365,22 @@ mmio_exit:
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// MMIO_EXIT.
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MOVD $0, R9
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MOVD R0, 0xffff000000001000(R9)
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B ·kernelExitToEl1(SB)
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RET
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// HaltAndResume halts execution and point the pointer to the resume function.
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TEXT ·HaltAndResume(SB),NOSPLIT,$0
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BL ·Halt(SB)
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B ·kernelExitToEl1(SB) // Resume.
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// HaltEl1SvcAndResume calls Hooks.KernelSyscall and resume.
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TEXT ·HaltEl1SvcAndResume(SB),NOSPLIT,$0
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WORD $0xd538d092 // MRS TPIDR_EL1, R18
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MOVD CPU_SELF(RSV_REG), R3 // Load vCPU.
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MOVD R3, 8(RSP) // First argument (vCPU).
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CALL ·kernelSyscall(SB) // Call the trampoline.
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B ·kernelExitToEl1(SB) // Resume.
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// Shutdown stops the guest.
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TEXT ·Shutdown(SB),NOSPLIT,$0
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// PSCI EVENT.
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MOVD $0x84000009, R0
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@ -429,6 +467,7 @@ TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
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TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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ERET()
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// Start is the CPU entrypoint.
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TEXT ·Start(SB),NOSPLIT,$0
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IRQ_DISABLE
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MOVD R8, RSV_REG
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@ -437,18 +476,23 @@ TEXT ·Start(SB),NOSPLIT,$0
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B ·kernelExitToEl1(SB)
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// El1_sync_invalid is the handler for an invalid EL1_sync.
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TEXT ·El1_sync_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_irq_invalid is the handler for an invalid El1_irq.
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TEXT ·El1_irq_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_fiq_invalid is the handler for an invalid El1_fiq.
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TEXT ·El1_fiq_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_error_invalid is the handler for an invalid El1_error.
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TEXT ·El1_error_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_sync is the handler for El1_sync.
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TEXT ·El1_sync(SB),NOSPLIT,$0
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KERNEL_ENTRY_FROM_EL1
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WORD $0xd5385219 // MRS ESR_EL1, R25
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@ -484,10 +528,10 @@ el1_da:
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MOVD $PageFault, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·Halt(SB)
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B ·HaltAndResume(SB)
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el1_ia:
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B ·Halt(SB)
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B ·HaltAndResume(SB)
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el1_sp_pc:
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B ·Shutdown(SB)
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@ -496,7 +540,9 @@ el1_undef:
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B ·Shutdown(SB)
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el1_svc:
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B ·Halt(SB)
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MOVD $0, CPU_ERROR_CODE(RSV_REG)
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MOVD $0, CPU_ERROR_TYPE(RSV_REG)
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B ·HaltEl1SvcAndResume(SB)
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el1_dbg:
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B ·Shutdown(SB)
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@ -508,15 +554,19 @@ el1_fpsimd_acc:
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el1_invalid:
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B ·Shutdown(SB)
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// El1_irq is the handler for El1_irq.
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TEXT ·El1_irq(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_fiq is the handler for El1_fiq.
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TEXT ·El1_fiq(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El1_error is the handler for El1_error.
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TEXT ·El1_error(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// El0_sync is the handler for El0_sync.
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TEXT ·El0_sync(SB),NOSPLIT,$0
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KERNEL_ENTRY_FROM_EL0
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WORD $0xd5385219 // MRS ESR_EL1, R25
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@ -554,7 +604,7 @@ el0_svc:
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MOVD $Syscall, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·Halt(SB)
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B ·HaltAndResume(SB)
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el0_da:
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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@ -568,7 +618,7 @@ el0_da:
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MOVD $PageFault, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·Halt(SB)
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B ·HaltAndResume(SB)
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el0_ia:
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B ·Shutdown(SB)
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@ -613,7 +663,7 @@ TEXT ·El0_error(SB),NOSPLIT,$0
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MOVD $VirtualizationException, R3
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MOVD R3, CPU_VECTOR_CODE(RSV_REG)
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B ·Halt(SB)
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B ·HaltAndResume(SB)
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TEXT ·El0_sync_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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@ -627,6 +677,7 @@ TEXT ·El0_fiq_invalid(SB),NOSPLIT,$0
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TEXT ·El0_error_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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// Vectors implements exception vector table.
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TEXT ·Vectors(SB),NOSPLIT,$0
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B ·El1_sync_invalid(SB)
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nop31Instructions()
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@ -16,6 +16,14 @@
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package ring0
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// HaltAndResume halts execution and point the pointer to the resume function.
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//go:nosplit
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func HaltAndResume()
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// HaltEl1SvcAndResume calls Hooks.KernelSyscall and resume.
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//go:nosplit
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func HaltEl1SvcAndResume()
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// init initializes architecture-specific state.
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func (k *Kernel) init(opts KernelOpts) {
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// Save the root page tables.
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