Add AMD-specific features to cpuid package
Extend the cpuid package to parse and emulate cpuid features that exist only on AMD and not Intel. The least straightforward part of this is that AMD duplicates several block 1 features in block 6. Thus we ignore those features when parsing block 6 and add them when emulating. PiperOrigin-RevId: 218935032 Change-Id: Id41bf1c24720b0d9b968e2c19ab5bc00a6d62bd4
This commit is contained in:
Michael Pratt
Shentubot
parent
e60525e4dd
commit
b15a7267e1
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@ -39,9 +39,20 @@ import (
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"gvisor.googlesource.com/gvisor/pkg/log"
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)
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// Common references for CPUID leaves and bits:
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//
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// Intel:
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// * Intel SDM Volume 2, Chapter 3.2 "CPUID" (more up-to-date)
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// * Intel Application Note 485 (more detailed)
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//
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// AMD:
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// * AMD64 APM Volume 3, Appendix 3 "Obtaining Processor Information ..."
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// Feature is a unique identifier for a particular cpu feature. We just use an
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// int as a feature number on x86. It corresponds to the bit position in the
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// basic feature mask returned by a cpuid with eax=1.
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// int as a feature number on x86.
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//
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// Features are numbered according to "blocks". Each block is 32 bits, and
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// feature bits from the same source (cpuid leaf/level) are in the same block.
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type Feature int
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// block is a collection of 32 Feature bits.
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@ -185,36 +196,60 @@ const (
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)
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// Block 5 constants are the extended feature bits in
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// CPUID.(EAX=0x80000001):ECX. These are very sparse, and so the bit positions
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// are assigned manually.
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// CPUID.(EAX=0x80000001):ECX.
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const (
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X86FeatureLAHF64 Feature = 5*32 + 0
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X86FeatureLZCNT Feature = 5*32 + 5
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X86FeaturePREFETCHW Feature = 5*32 + 8
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X86FeatureLAHF64 Feature = 5*32 + iota
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X86FeatureCMP_LEGACY
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X86FeatureSVM
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X86FeatureEXTAPIC
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X86FeatureCR8_LEGACY
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X86FeatureLZCNT
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X86FeatureSSE4A
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X86FeatureMISALIGNSSE
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X86FeaturePREFETCHW
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X86FeatureOSVW
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X86FeatureIBS
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X86FeatureXOP
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X86FeatureSKINIT
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X86FeatureWDT
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_ // ecx bit 14 is reserved.
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X86FeatureLWP
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X86FeatureFMA4
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X86FeatureTCE
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_ // ecx bit 18 is reserved.
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_ // ecx bit 19 is reserved.
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_ // ecx bit 20 is reserved.
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X86FeatureTBM
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X86FeatureTOPOLOGY
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X86FeaturePERFCTR_CORE
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X86FeaturePERFCTR_NB
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_ // ecx bit 25 is reserved.
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X86FeatureBPEXT
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X86FeaturePERFCTR_TSC
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X86FeaturePERFCTR_L2
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X86FeatureMWAITX
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// ECX[31:30] are reserved.
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)
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// Block 6 constants are the extended feature bits in
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// CPUID.(EAX=0x80000001):EDX. These are very sparse, and so the bit positions
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// are assigned manually.
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// CPUID.(EAX=0x80000001):EDX.
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//
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// These are sparse, and so the bit positions are assigned manually.
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const (
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X86FeatureSYSCALL Feature = 6*32 + 11
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X86FeatureNX Feature = 6*32 + 20
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X86FeatureGBPAGES Feature = 6*32 + 26
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X86FeatureRDTSCP Feature = 6*32 + 27
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X86FeatureLM Feature = 6*32 + 29
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// These are not in the most recent intel manual. Not surprising... It
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// shouldn't matter but we should find where these bits come from and
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// support them. The linux strings are below for completeness.
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//X86FeatureMMXEXT
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//X86FeatureMP
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//X86FeatureFXSR_OPT
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//X86Feature3DNOWEXT
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//X86Feature3DNOW
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//X86FeatureMMXEXT: "mmxext",
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//X86FeatureMP: "mp",
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//X86FeatureFXSR_OPT: "fxsr_opt",
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//X86Feature3DNOWEXT: "3dnowext",
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//X86Feature3DNOW: "3dnow",
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// On AMD, EDX[24:23] | EDX[17:12] | EDX[9:0] are duplicate features
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// also defined in block 1 (in identical bit positions). Those features
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// are not listed here.
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block6DuplicateMask = 0x183f3ff
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X86FeatureSYSCALL Feature = 6*32 + 11
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X86FeatureNX Feature = 6*32 + 20
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X86FeatureMMXEXT Feature = 6*32 + 22
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X86FeatureFXSR_OPT Feature = 6*32 + 25
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X86FeatureGBPAGES Feature = 6*32 + 26
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X86FeatureRDTSCP Feature = 6*32 + 27
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X86FeatureLM Feature = 6*32 + 29
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X86Feature3DNOWEXT Feature = 6*32 + 30
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X86Feature3DNOW Feature = 6*32 + 31
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)
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// linuxBlockOrder defines the order in which linux organizes the feature
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@ -224,9 +259,8 @@ const (
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// block.
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var linuxBlockOrder = []block{1, 6, 0, 5, 2, 4, 3}
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// To make emulation of /proc/cpuinfo easy down the line, these names match the
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// names of the basic features in Linux defined in
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// arch/x86/kernel/cpu/capflags.c.
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// To make emulation of /proc/cpuinfo easy, these names match the names of the
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// basic features in Linux defined in arch/x86/kernel/cpu/capflags.c.
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var x86FeatureStrings = map[Feature]string{
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// Block 0.
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X86FeatureSSE3: "pni",
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@ -329,16 +363,42 @@ var x86FeatureStrings = map[Feature]string{
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X86FeatureXGETBV1: "xgetbv1",
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// Block 5.
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X86FeatureLAHF64: "lahf_lm", // LAHF/SAHF in long mode
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X86FeatureLZCNT: "abm", // Advanced bit manipulation
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X86FeaturePREFETCHW: "3dnowprefetch",
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X86FeatureLAHF64: "lahf_lm", // LAHF/SAHF in long mode
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X86FeatureCMP_LEGACY: "cmp_legacy",
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X86FeatureSVM: "svm",
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X86FeatureEXTAPIC: "extapic",
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X86FeatureCR8_LEGACY: "cr8_legacy",
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X86FeatureLZCNT: "abm", // Advanced bit manipulation
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X86FeatureSSE4A: "sse4a",
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X86FeatureMISALIGNSSE: "misalignsse",
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X86FeaturePREFETCHW: "3dnowprefetch",
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X86FeatureOSVW: "osvw",
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X86FeatureIBS: "ibs",
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X86FeatureXOP: "xop",
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X86FeatureSKINIT: "skinit",
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X86FeatureWDT: "wdt",
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X86FeatureLWP: "lwp",
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X86FeatureFMA4: "fma4",
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X86FeatureTCE: "tce",
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X86FeatureTBM: "tbm",
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X86FeatureTOPOLOGY: "topoext",
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X86FeaturePERFCTR_CORE: "perfctr_core",
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X86FeaturePERFCTR_NB: "perfctr_nb",
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X86FeatureBPEXT: "bpext",
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X86FeaturePERFCTR_TSC: "ptsc",
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X86FeaturePERFCTR_L2: "perfctr_l2",
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X86FeatureMWAITX: "mwaitx",
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// Block 6.
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X86FeatureSYSCALL: "syscall",
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X86FeatureNX: "nx",
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X86FeatureGBPAGES: "pdpe1gb",
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X86FeatureRDTSCP: "rdtscp",
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X86FeatureLM: "lm",
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X86FeatureSYSCALL: "syscall",
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X86FeatureNX: "nx",
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X86FeatureMMXEXT: "mmxext",
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X86FeatureFXSR_OPT: "fxsr_opt",
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X86FeatureGBPAGES: "pdpe1gb",
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X86FeatureRDTSCP: "rdtscp",
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X86FeatureLM: "lm",
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X86Feature3DNOWEXT: "3dnowext",
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X86Feature3DNOW: "3dnow",
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}
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// These flags are parse only---they can be used for setting / unsetting the
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@ -358,44 +418,29 @@ var x86FeatureParseOnlyStrings = map[Feature]string{
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X86FeatureXSAVES: "xsaves",
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}
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// These are the default values of various FeatureSet fields.
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const (
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defaultVendorID = "GenuineIntel"
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// These processor signature defaults are derived from the values
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// listed in Intel AN485 for i7/Xeon processors.
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defaultExtFamily uint8 = 0
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defaultExtModel uint8 = 1
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defaultType uint8 = 0
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defaultFamily uint8 = 0x06
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defaultModel uint8 = 0x0a
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defaultSteppingID uint8 = 0
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)
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// Just a way to wrap cpuid function numbers.
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type cpuidFunction uint32
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// The constants below are the lower or "standard" cpuid functions. See Intel
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// AN485 for detailed information about each one.
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// The constants below are the lower or "standard" cpuid functions, ordered as
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// defined by the hardware.
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const (
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vendorID cpuidFunction = iota // Returns vendor ID and largest standard function.
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featureInfo // Returns basic feature bits and processor signature.
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cacheDescriptors // Returns list of cache descriptors.
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serialNumber // Returns processor serial number (obsolete on new hardware).
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deterministicCacheParams // Returns deterministic cache information. See AN485.
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monitorMwaitParams // Returns information about monitor/mwait instructions.
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powerParams // Returns information about power management and thermal sensors.
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extendedFeatureInfo // Returns extended feature bits.
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_ // Function 8 is reserved.
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DCAParams // Returns direct cache access information.
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pmcInfo // Returns information about performance monitoring features.
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x2APICInfo // Returns core/logical processor topology. See AN485 for details.
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_ // Function 0xc is reserved.
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xSaveInfo // Returns information about extended state management.
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vendorID cpuidFunction = iota // Returns vendor ID and largest standard function.
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featureInfo // Returns basic feature bits and processor signature.
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intelCacheDescriptors // Returns list of cache descriptors. Intel only.
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intelSerialNumber // Returns processor serial number (obsolete on new hardware). Intel only.
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intelDeterministicCacheParams // Returns deterministic cache information. Intel only.
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monitorMwaitParams // Returns information about monitor/mwait instructions.
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powerParams // Returns information about power management and thermal sensors.
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extendedFeatureInfo // Returns extended feature bits.
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_ // Function 0x8 is reserved.
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intelDCAParams // Returns direct cache access information. Intel only.
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intelPMCInfo // Returns information about performance monitoring features. Intel only.
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intelX2APICInfo // Returns core/logical processor topology. Intel only.
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_ // Function 0xc is reserved.
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xSaveInfo // Returns information about extended state management.
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)
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// The "extended" functions start at 0x80000000. Intel AP-485 has information
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// on these as well.
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// The "extended" functions start at 0x80000000.
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const (
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extendedFunctionInfo cpuidFunction = 0x80000000 + iota // Returns highest available extended function in eax.
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extendedFeatures // Returns some extended feature bits in edx and ecx.
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@ -419,7 +464,10 @@ func (f Feature) String() string {
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if s := f.flagString(false); s != "" {
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return s
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}
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return fmt.Sprintf("<cpuflag %d>", f)
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block := int(f) / 32
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bit := int(f) % 32
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return fmt.Sprintf("<cpuflag %d; block %d bit %d>", f, block, bit)
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}
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func (f Feature) flagString(cpuinfoOnly bool) string {
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@ -597,27 +645,6 @@ func signatureSplit(v uint32) (ef, em, pt, f, m, sid uint8) {
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return
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}
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// This factory function is only needed inside the package, package users
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// should not be creating and using empty feature sets.
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func newEmptyFeatureSet() *FeatureSet {
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return newFeatureSet(make(map[Feature]bool))
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}
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// newFeatureSet creates a new FeatureSet with sensible default values and the
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// provided set of features.
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func newFeatureSet(s map[Feature]bool) *FeatureSet {
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return &FeatureSet{
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Set: s,
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VendorID: defaultVendorID,
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ExtendedFamily: defaultExtFamily,
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ExtendedModel: defaultExtModel,
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ProcessorType: defaultType,
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Family: defaultFamily,
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Model: defaultModel,
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SteppingID: defaultSteppingID,
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}
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}
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// Helper to convert blockwise feature bit masks into a set of features. Masks
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// must be provided in order for each block, without skipping them. If a block
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// does not matter for this feature set, 0 is specified.
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@ -726,6 +753,10 @@ func (fs *FeatureSet) EmulateID(origAx, origCx uint32) (ax, bx, cx, dx uint32) {
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case extendedFeatures:
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cx = fs.blockMask(block(5))
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dx = fs.blockMask(block(6))
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if fs.VendorID == "AuthenticAMD" {
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// AMD duplicates some block 1 features in block 6.
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dx |= fs.blockMask(block(1)) & block6DuplicateMask
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}
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}
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return
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@ -779,7 +810,9 @@ func HostFeatureSet() *FeatureSet {
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// eax=0x80000001 gets AMD added feature bits.
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_, _, cx, dx = HostID(uint32(extendedFeatures), 0)
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featureBlock5 = cx
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featureBlock6 = dx
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// Ignore features duplicated from block 1 on AMD. These bits
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// are reserved on Intel.
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featureBlock6 = dx &^ block6DuplicateMask
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}
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set := setFromBlockMasks(featureBlock0, featureBlock1, featureBlock2, featureBlock3, featureBlock4, featureBlock5, featureBlock6)
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@ -810,7 +843,7 @@ func initCPUFreq() {
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// We get the value straight from host /proc/cpuinfo. On machines with
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// frequency scaling enabled, this will only get the current value
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// which will likely be innacurate. This is fine on machines with
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// which will likely be inaccurate. This is fine on machines with
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// frequency scaling disabled.
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for _, line := range strings.Split(cpuinfo, "\n") {
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if strings.Contains(line, "cpu MHz") {
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@ -18,6 +18,34 @@ import (
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"testing"
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)
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// These are the default values of various FeatureSet fields.
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const (
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defaultVendorID = "GenuineIntel"
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// These processor signature defaults are derived from the values
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// listed in Intel Application Note 485 for i7/Xeon processors.
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defaultExtFamily uint8 = 0
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defaultExtModel uint8 = 1
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defaultType uint8 = 0
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defaultFamily uint8 = 0x06
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defaultModel uint8 = 0x0a
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defaultSteppingID uint8 = 0
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)
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// newEmptyFeatureSet creates a new FeatureSet with a sensible default model and no features.
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func newEmptyFeatureSet() *FeatureSet {
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return &FeatureSet{
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Set: make(map[Feature]bool),
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VendorID: defaultVendorID,
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ExtendedFamily: defaultExtFamily,
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ExtendedModel: defaultExtModel,
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ProcessorType: defaultType,
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Family: defaultFamily,
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Model: defaultModel,
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SteppingID: defaultSteppingID,
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}
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}
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var justFPU = &FeatureSet{
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Set: map[Feature]bool{
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X86FeatureFPU: true,
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