165 lines
4.7 KiB
Go
165 lines
4.7 KiB
Go
// Copyright 2019 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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package kvm
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// KVM ioctls for Arm64.
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const (
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_KVM_GET_ONE_REG = 0x4010aeab
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_KVM_SET_ONE_REG = 0x4010aeac
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_KVM_ARM_TARGET_GENERIC_V8 = 5
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_KVM_ARM_PREFERRED_TARGET = 0x8020aeaf
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_KVM_ARM_VCPU_INIT = 0x4020aeae
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_KVM_ARM64_REGS_PSTATE = 0x6030000000100042
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_KVM_ARM64_REGS_SP_EL1 = 0x6030000000100044
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_KVM_ARM64_REGS_R0 = 0x6030000000100000
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_KVM_ARM64_REGS_R1 = 0x6030000000100002
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_KVM_ARM64_REGS_R2 = 0x6030000000100004
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_KVM_ARM64_REGS_R3 = 0x6030000000100006
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_KVM_ARM64_REGS_R8 = 0x6030000000100010
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_KVM_ARM64_REGS_R18 = 0x6030000000100024
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_KVM_ARM64_REGS_PC = 0x6030000000100040
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_KVM_ARM64_REGS_MAIR_EL1 = 0x603000000013c510
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_KVM_ARM64_REGS_TCR_EL1 = 0x603000000013c102
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_KVM_ARM64_REGS_TTBR0_EL1 = 0x603000000013c100
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_KVM_ARM64_REGS_TTBR1_EL1 = 0x603000000013c101
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_KVM_ARM64_REGS_SCTLR_EL1 = 0x603000000013c080
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_KVM_ARM64_REGS_CPACR_EL1 = 0x603000000013c082
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_KVM_ARM64_REGS_VBAR_EL1 = 0x603000000013c600
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_KVM_ARM64_REGS_TIMER_CNT = 0x603000000013df1a
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_KVM_ARM64_REGS_CNTFRQ_EL0 = 0x603000000013df00
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)
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// Arm64: Architectural Feature Access Control Register EL1.
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const (
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_FPEN_NOTRAP = 3
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_FPEN_SHIFT = 20
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)
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// Arm64: System Control Register EL1.
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const (
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_SCTLR_M = 1 << 0
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_SCTLR_C = 1 << 2
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_SCTLR_I = 1 << 12
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)
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// Arm64: Translation Control Register EL1.
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const (
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_TCR_IPS_40BITS = 2 << 32 // PA=40
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_TCR_IPS_48BITS = 5 << 32 // PA=48
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_TCR_T0SZ_OFFSET = 0
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_TCR_T1SZ_OFFSET = 16
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_TCR_IRGN0_SHIFT = 8
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_TCR_IRGN1_SHIFT = 24
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_TCR_ORGN0_SHIFT = 10
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_TCR_ORGN1_SHIFT = 26
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_TCR_SH0_SHIFT = 12
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_TCR_SH1_SHIFT = 28
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_TCR_TG0_SHIFT = 14
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_TCR_TG1_SHIFT = 30
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_TCR_T0SZ_VA48 = 64 - 48 // VA=48
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_TCR_T1SZ_VA48 = 64 - 48 // VA=48
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_TCR_A1 = 1 << 22
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_TCR_ASID16 = 1 << 36
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_TCR_TBI0 = 1 << 37
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_TCR_TXSZ_VA48 = (_TCR_T0SZ_VA48 << _TCR_T0SZ_OFFSET) | (_TCR_T1SZ_VA48 << _TCR_T1SZ_OFFSET)
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_TCR_TG0_4K = 0 << _TCR_TG0_SHIFT // 4K
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_TCR_TG0_64K = 1 << _TCR_TG0_SHIFT // 64K
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_TCR_TG1_4K = 2 << _TCR_TG1_SHIFT
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_TCR_TG_FLAGS = _TCR_TG0_4K | _TCR_TG1_4K
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_TCR_IRGN0_WBWA = 1 << _TCR_IRGN0_SHIFT
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_TCR_IRGN1_WBWA = 1 << _TCR_IRGN1_SHIFT
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_TCR_IRGN_WBWA = _TCR_IRGN0_WBWA | _TCR_IRGN1_WBWA
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_TCR_ORGN0_WBWA = 1 << _TCR_ORGN0_SHIFT
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_TCR_ORGN1_WBWA = 1 << _TCR_ORGN1_SHIFT
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_TCR_ORGN_WBWA = _TCR_ORGN0_WBWA | _TCR_ORGN1_WBWA
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_TCR_SHARED = (3 << _TCR_SH0_SHIFT) | (3 << _TCR_SH1_SHIFT)
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_TCR_CACHE_FLAGS = _TCR_IRGN_WBWA | _TCR_ORGN_WBWA
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)
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// Arm64: Memory Attribute Indirection Register EL1.
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const (
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_MT_DEVICE_nGnRnE = 0
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_MT_DEVICE_nGnRE = 1
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_MT_DEVICE_GRE = 2
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_MT_NORMAL_NC = 3
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_MT_NORMAL = 4
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_MT_NORMAL_WT = 5
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_MT_ATTR_DEVICE_nGnRnE = 0x00
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_MT_ATTR_DEVICE_nGnRE = 0x04
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_MT_ATTR_DEVICE_GRE = 0x0c
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_MT_ATTR_NORMAL_NC = 0x44
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_MT_ATTR_NORMAL_WT = 0xbb
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_MT_ATTR_NORMAL = 0xff
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_MT_ATTR_MASK = 0xff
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_MT_EL1_INIT = (_MT_ATTR_DEVICE_nGnRnE << (_MT_DEVICE_nGnRnE * 8)) | (_MT_ATTR_DEVICE_nGnRE << (_MT_DEVICE_nGnRE * 8)) | (_MT_ATTR_DEVICE_GRE << (_MT_DEVICE_GRE * 8)) | (_MT_ATTR_NORMAL_NC << (_MT_NORMAL_NC * 8)) | (_MT_ATTR_NORMAL << (_MT_NORMAL * 8)) | (_MT_ATTR_NORMAL_WT << (_MT_NORMAL_WT * 8))
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)
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const (
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_KVM_ARM_VCPU_POWER_OFF = 0 // CPU is started in OFF state
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_KVM_ARM_VCPU_PSCI_0_2 = 2 // CPU uses PSCI v0.2
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)
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// Arm64: Exception Syndrome Register EL1.
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const (
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_ESR_ELx_EC_SHIFT = 26
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_ESR_ELx_EC_MASK = 0x3F << _ESR_ELx_EC_SHIFT
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_ESR_ELx_EC_IMP_DEF = 0x1f
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_ESR_ELx_EC_IABT_LOW = 0x20
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_ESR_ELx_EC_IABT_CUR = 0x21
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_ESR_ELx_EC_PC_ALIGN = 0x22
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_ESR_ELx_CM = 1 << 8
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_ESR_ELx_WNR = 1 << 6
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_ESR_ELx_FSC = 0x3F
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_ESR_SEGV_MAPERR_L0 = 0x4
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_ESR_SEGV_MAPERR_L1 = 0x5
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_ESR_SEGV_MAPERR_L2 = 0x6
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_ESR_SEGV_MAPERR_L3 = 0x7
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_ESR_SEGV_ACCERR_L1 = 0x9
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_ESR_SEGV_ACCERR_L2 = 0xa
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_ESR_SEGV_ACCERR_L3 = 0xb
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_ESR_SEGV_PEMERR_L1 = 0xd
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_ESR_SEGV_PEMERR_L2 = 0xe
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_ESR_SEGV_PEMERR_L3 = 0xf
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// Custom ISS field definitions for system error.
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_ESR_ELx_SERR_NMI = 0x1
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)
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// Arm64: MMIO base address used to dispatch hypercalls.
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const (
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// on Arm64, the MMIO address must be 64-bit aligned.
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// Currently, we only need 1 hypercall: hypercall_vmexit.
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_AARCH64_HYPERCALL_MMIO_SIZE = 1 << 3
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)
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