592 lines
15 KiB
ArmAsm
592 lines
15 KiB
ArmAsm
// Copyright 2019 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "funcdata.h"
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#include "textflag.h"
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// NB: Offsets are programatically generated (see BUILD).
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//
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// This file is concatenated with the definitions.
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// Saves a register set.
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//
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// This is a macro because it may need to executed in contents where a stack is
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// not available for calls.
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//
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#define ERET() \
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WORD $0xd69f03e0
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#define RSV_REG R18_PLATFORM
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#define RSV_REG_APP R9
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#define FPEN_NOTRAP 0x3
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#define FPEN_SHIFT 20
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#define FPEN_ENABLE (FPEN_NOTRAP << FPEN_SHIFT)
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#define REGISTERS_SAVE(reg, offset) \
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MOVD R0, offset+PTRACE_R0(reg); \
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MOVD R1, offset+PTRACE_R1(reg); \
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MOVD R2, offset+PTRACE_R2(reg); \
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MOVD R3, offset+PTRACE_R3(reg); \
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MOVD R4, offset+PTRACE_R4(reg); \
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MOVD R5, offset+PTRACE_R5(reg); \
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MOVD R6, offset+PTRACE_R6(reg); \
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MOVD R7, offset+PTRACE_R7(reg); \
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MOVD R8, offset+PTRACE_R8(reg); \
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MOVD R10, offset+PTRACE_R10(reg); \
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MOVD R11, offset+PTRACE_R11(reg); \
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MOVD R12, offset+PTRACE_R12(reg); \
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MOVD R13, offset+PTRACE_R13(reg); \
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MOVD R14, offset+PTRACE_R14(reg); \
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MOVD R15, offset+PTRACE_R15(reg); \
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MOVD R16, offset+PTRACE_R16(reg); \
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MOVD R17, offset+PTRACE_R17(reg); \
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MOVD R19, offset+PTRACE_R19(reg); \
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MOVD R20, offset+PTRACE_R20(reg); \
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MOVD R21, offset+PTRACE_R21(reg); \
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MOVD R22, offset+PTRACE_R22(reg); \
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MOVD R23, offset+PTRACE_R23(reg); \
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MOVD R24, offset+PTRACE_R24(reg); \
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MOVD R25, offset+PTRACE_R25(reg); \
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MOVD R26, offset+PTRACE_R26(reg); \
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MOVD R27, offset+PTRACE_R27(reg); \
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MOVD g, offset+PTRACE_R28(reg); \
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MOVD R29, offset+PTRACE_R29(reg); \
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MOVD R30, offset+PTRACE_R30(reg);
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#define REGISTERS_LOAD(reg, offset) \
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MOVD offset+PTRACE_R0(reg), R0; \
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MOVD offset+PTRACE_R1(reg), R1; \
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MOVD offset+PTRACE_R2(reg), R2; \
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MOVD offset+PTRACE_R3(reg), R3; \
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MOVD offset+PTRACE_R4(reg), R4; \
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MOVD offset+PTRACE_R5(reg), R5; \
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MOVD offset+PTRACE_R6(reg), R6; \
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MOVD offset+PTRACE_R7(reg), R7; \
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MOVD offset+PTRACE_R8(reg), R8; \
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MOVD offset+PTRACE_R10(reg), R10; \
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MOVD offset+PTRACE_R11(reg), R11; \
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MOVD offset+PTRACE_R12(reg), R12; \
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MOVD offset+PTRACE_R13(reg), R13; \
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MOVD offset+PTRACE_R14(reg), R14; \
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MOVD offset+PTRACE_R15(reg), R15; \
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MOVD offset+PTRACE_R16(reg), R16; \
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MOVD offset+PTRACE_R17(reg), R17; \
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MOVD offset+PTRACE_R19(reg), R19; \
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MOVD offset+PTRACE_R20(reg), R20; \
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MOVD offset+PTRACE_R21(reg), R21; \
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MOVD offset+PTRACE_R22(reg), R22; \
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MOVD offset+PTRACE_R23(reg), R23; \
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MOVD offset+PTRACE_R24(reg), R24; \
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MOVD offset+PTRACE_R25(reg), R25; \
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MOVD offset+PTRACE_R26(reg), R26; \
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MOVD offset+PTRACE_R27(reg), R27; \
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MOVD offset+PTRACE_R28(reg), g; \
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MOVD offset+PTRACE_R29(reg), R29; \
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MOVD offset+PTRACE_R30(reg), R30;
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//NOP
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#define nop31Instructions() \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f; \
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WORD $0xd503201f;
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#define ESR_ELx_EC_UNKNOWN (0x00)
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#define ESR_ELx_EC_WFx (0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELx_EC_CP15_32 (0x03)
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#define ESR_ELx_EC_CP15_64 (0x04)
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#define ESR_ELx_EC_CP14_MR (0x05)
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#define ESR_ELx_EC_CP14_LS (0x06)
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#define ESR_ELx_EC_FP_ASIMD (0x07)
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#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
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#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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#define ESR_ELx_EC_CP14_64 (0x0C)
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/* Unallocated EC: 0x0d */
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#define ESR_ELx_EC_ILL (0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELx_EC_SVC32 (0x11)
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#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
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#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
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/* Unallocated EC: 0x14 */
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#define ESR_ELx_EC_SVC64 (0x15)
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#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
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#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
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#define ESR_ELx_EC_SYS64 (0x18)
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#define ESR_ELx_EC_SVE (0x19)
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/* Unallocated EC: 0x1A - 0x1E */
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#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
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#define ESR_ELx_EC_IABT_LOW (0x20)
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#define ESR_ELx_EC_IABT_CUR (0x21)
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#define ESR_ELx_EC_PC_ALIGN (0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELx_EC_DABT_LOW (0x24)
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#define ESR_ELx_EC_DABT_CUR (0x25)
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#define ESR_ELx_EC_SP_ALIGN (0x26)
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/* Unallocated EC: 0x27 */
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#define ESR_ELx_EC_FP_EXC32 (0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELx_EC_FP_EXC64 (0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELx_EC_SERROR (0x2F)
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#define ESR_ELx_EC_BREAKPT_LOW (0x30)
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#define ESR_ELx_EC_BREAKPT_CUR (0x31)
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#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
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#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
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#define ESR_ELx_EC_WATCHPT_LOW (0x34)
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#define ESR_ELx_EC_WATCHPT_CUR (0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELx_EC_BKPT32 (0x38)
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/* Unallocated EC: 0x39 */
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#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
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/* Unallocted EC: 0x3B */
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#define ESR_ELx_EC_BRK64 (0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELx_EC_MAX (0x3F)
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#define ESR_ELx_EC_SHIFT (26)
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#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
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#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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#define ESR_ELx_IL_SHIFT (25)
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#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
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#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
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/* ISS field definitions shared by different classes */
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#define ESR_ELx_WNR_SHIFT (6)
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#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
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/* Asynchronous Error Type */
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#define ESR_ELx_IDS_SHIFT (24)
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#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
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#define ESR_ELx_AET_SHIFT (10)
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#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
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/* Shared ISS field definitions for Data/Instruction aborts */
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#define ESR_ELx_SET_SHIFT (11)
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#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
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#define ESR_ELx_FnV_SHIFT (10)
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#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
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#define ESR_ELx_EA_SHIFT (9)
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#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
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#define ESR_ELx_S1PTW_SHIFT (7)
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#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_SERROR (0x11)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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/* ISS field definitions for Data Aborts */
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#define ESR_ELx_ISV_SHIFT (24)
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#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
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#define ESR_ELx_SAS_SHIFT (22)
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#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
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#define ESR_ELx_SSE_SHIFT (21)
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#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
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#define ESR_ELx_SRT_SHIFT (16)
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#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
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#define ESR_ELx_SF_SHIFT (15)
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#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
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#define ESR_ELx_AR_SHIFT (14)
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#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
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#define ESR_ELx_CM_SHIFT (8)
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#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
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/* ISS field definitions for exceptions taken in to Hyp */
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#define ESR_ELx_CV (UL(1) << 24)
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#define ESR_ELx_COND_SHIFT (20)
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#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
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#define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
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#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
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#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
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#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
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#define LOAD_KERNEL_ADDRESS(from, to) \
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MOVD from, to; \
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ORR $0xffff000000000000, to, to;
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// LOAD_KERNEL_STACK loads the kernel temporary stack.
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#define LOAD_KERNEL_STACK(from) \
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LOAD_KERNEL_ADDRESS(CPU_SELF(from), RSV_REG); \
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MOVD $CPU_STACK_TOP(RSV_REG), RSV_REG; \
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MOVD RSV_REG, RSP; \
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ISB $15; \
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DSB $15;
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#define SWITCH_TO_APP_PAGETABLE(from) \
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MOVD CPU_TTBR0_APP(from), RSV_REG; \
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WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
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ISB $15; \
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DSB $15;
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#define SWITCH_TO_KVM_PAGETABLE(from) \
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MOVD CPU_TTBR0_KVM(from), RSV_REG; \
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WORD $0xd5182012; \ // MSR R18, TTBR0_EL1
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ISB $15; \
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DSB $15;
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#define IRQ_ENABLE \
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MSR $2, DAIFSet;
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#define IRQ_DISABLE \
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MSR $2, DAIFClr;
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#define VFP_ENABLE \
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MOVD $FPEN_ENABLE, R0; \
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WORD $0xd5181040; \ //MSR R0, CPACR_EL1
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ISB $15;
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#define VFP_DISABLE \
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MOVD $0x0, R0; \
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WORD $0xd5181040; \ //MSR R0, CPACR_EL1
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ISB $15;
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#define KERNEL_ENTRY_FROM_EL0 \
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SUB $16, RSP, RSP; \ // step1, save r18, r9 into kernel temporary stack.
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STP (RSV_REG, RSV_REG_APP), 16*0(RSP); \
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WORD $0xd538d092; \ //MRS TPIDR_EL1, R18, step2, switch user pagetable.
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SWITCH_TO_KVM_PAGETABLE(RSV_REG); \
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WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
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MOVD CPU_APP_ADDR(RSV_REG), RSV_REG_APP; \ // step3, load app context pointer.
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REGISTERS_SAVE(RSV_REG_APP, 0); \ // step4, save app context.
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MOVD RSV_REG_APP, R20; \
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LDP 16*0(RSP), (RSV_REG, RSV_REG_APP); \
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ADD $16, RSP, RSP; \
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MOVD RSV_REG, PTRACE_R18(R20); \
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MOVD RSV_REG_APP, PTRACE_R9(R20); \
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MOVD R20, RSV_REG_APP; \
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WORD $0xd5384003; \ // MRS SPSR_EL1, R3
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MOVD R3, PTRACE_PSTATE(RSV_REG_APP); \
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MRS ELR_EL1, R3; \
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MOVD R3, PTRACE_PC(RSV_REG_APP); \
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WORD $0xd5384103; \ // MRS SP_EL0, R3
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MOVD R3, PTRACE_SP(RSV_REG_APP);
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#define KERNEL_ENTRY_FROM_EL1 \
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WORD $0xd538d092; \ //MRS TPIDR_EL1, R18
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REGISTERS_SAVE(RSV_REG, CPU_REGISTERS); \ // save sentry context
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MOVD RSV_REG_APP, CPU_REGISTERS+PTRACE_R9(RSV_REG); \
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WORD $0xd5384004; \ // MRS SPSR_EL1, R4
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MOVD R4, CPU_REGISTERS+PTRACE_PSTATE(RSV_REG); \
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MRS ELR_EL1, R4; \
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MOVD R4, CPU_REGISTERS+PTRACE_PC(RSV_REG); \
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MOVD RSP, R4; \
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MOVD R4, CPU_REGISTERS+PTRACE_SP(RSV_REG);
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TEXT ·Halt(SB),NOSPLIT,$0
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// clear bluepill.
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WORD $0xd538d092 //MRS TPIDR_EL1, R18
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CMP RSV_REG, R9
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BNE mmio_exit
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MOVD $0, CPU_REGISTERS+PTRACE_R9(RSV_REG)
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mmio_exit:
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// Disable fpsimd.
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WORD $0xd5381041 // MRS CPACR_EL1, R1
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MOVD R1, CPU_LAZY_VFP(RSV_REG)
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VFP_DISABLE
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// MMIO_EXIT.
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MOVD $0, R9
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MOVD R0, 0xffff000000001000(R9)
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B ·kernelExitToEl1(SB)
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TEXT ·Shutdown(SB),NOSPLIT,$0
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// PSCI EVENT.
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MOVD $0x84000009, R0
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HVC $0
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// See kernel.go.
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TEXT ·Current(SB),NOSPLIT,$0-8
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MOVD CPU_SELF(RSV_REG), R8
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MOVD R8, ret+0(FP)
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RET
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#define STACK_FRAME_SIZE 16
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TEXT ·kernelExitToEl0(SB),NOSPLIT,$0
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ERET()
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TEXT ·kernelExitToEl1(SB),NOSPLIT,$0
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ERET()
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TEXT ·Start(SB),NOSPLIT,$0
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IRQ_DISABLE
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MOVD R8, RSV_REG
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ORR $0xffff000000000000, RSV_REG, RSV_REG
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WORD $0xd518d092 //MSR R18, TPIDR_EL1
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B ·kernelExitToEl1(SB)
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TEXT ·El1_sync_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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TEXT ·El1_irq_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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TEXT ·El1_fiq_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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TEXT ·El1_error_invalid(SB),NOSPLIT,$0
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B ·Shutdown(SB)
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TEXT ·El1_sync(SB),NOSPLIT,$0
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KERNEL_ENTRY_FROM_EL1
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WORD $0xd5385219 // MRS ESR_EL1, R25
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LSR $ESR_ELx_EC_SHIFT, R25, R24
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CMP $ESR_ELx_EC_DABT_CUR, R24
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BEQ el1_da
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CMP $ESR_ELx_EC_IABT_CUR, R24
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BEQ el1_ia
|
|
CMP $ESR_ELx_EC_SYS64, R24
|
|
BEQ el1_undef
|
|
CMP $ESR_ELx_EC_SP_ALIGN, R24
|
|
BEQ el1_sp_pc
|
|
CMP $ESR_ELx_EC_PC_ALIGN, R24
|
|
BEQ el1_sp_pc
|
|
CMP $ESR_ELx_EC_UNKNOWN, R24
|
|
BEQ el1_undef
|
|
CMP $ESR_ELx_EC_SVC64, R24
|
|
BEQ el1_svc
|
|
CMP $ESR_ELx_EC_BREAKPT_CUR, R24
|
|
BGE el1_dbg
|
|
CMP $ESR_ELx_EC_FP_ASIMD, R24
|
|
BEQ el1_fpsimd_acc
|
|
B el1_invalid
|
|
|
|
el1_da:
|
|
B ·Halt(SB)
|
|
|
|
el1_ia:
|
|
B ·Halt(SB)
|
|
|
|
el1_sp_pc:
|
|
B ·Shutdown(SB)
|
|
|
|
el1_undef:
|
|
B ·Shutdown(SB)
|
|
|
|
el1_svc:
|
|
B ·Halt(SB)
|
|
|
|
el1_dbg:
|
|
B ·Shutdown(SB)
|
|
|
|
el1_fpsimd_acc:
|
|
VFP_ENABLE
|
|
B ·kernelExitToEl1(SB) // Resume.
|
|
|
|
el1_invalid:
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El1_irq(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El1_fiq(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El1_error(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_sync(SB),NOSPLIT,$0
|
|
KERNEL_ENTRY_FROM_EL0
|
|
WORD $0xd5385219 // MRS ESR_EL1, R25
|
|
LSR $ESR_ELx_EC_SHIFT, R25, R24
|
|
CMP $ESR_ELx_EC_SVC64, R24
|
|
BEQ el0_svc
|
|
CMP $ESR_ELx_EC_DABT_LOW, R24
|
|
BEQ el0_da
|
|
CMP $ESR_ELx_EC_IABT_LOW, R24
|
|
BEQ el0_ia
|
|
CMP $ESR_ELx_EC_FP_ASIMD, R24
|
|
BEQ el0_fpsimd_acc
|
|
CMP $ESR_ELx_EC_SVE, R24
|
|
BEQ el0_sve_acc
|
|
CMP $ESR_ELx_EC_FP_EXC64, R24
|
|
BEQ el0_fpsimd_exc
|
|
CMP $ESR_ELx_EC_SP_ALIGN, R24
|
|
BEQ el0_sp_pc
|
|
CMP $ESR_ELx_EC_PC_ALIGN, R24
|
|
BEQ el0_sp_pc
|
|
CMP $ESR_ELx_EC_UNKNOWN, R24
|
|
BEQ el0_undef
|
|
CMP $ESR_ELx_EC_BREAKPT_LOW, R24
|
|
BGE el0_dbg
|
|
B el0_invalid
|
|
|
|
el0_svc:
|
|
B ·Halt(SB)
|
|
|
|
el0_da:
|
|
B ·Halt(SB)
|
|
|
|
el0_ia:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_fpsimd_acc:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_sve_acc:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_fpsimd_exc:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_sp_pc:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_undef:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_dbg:
|
|
B ·Shutdown(SB)
|
|
|
|
el0_invalid:
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_irq(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_fiq(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_error(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_sync_invalid(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_irq_invalid(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_fiq_invalid(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·El0_error_invalid(SB),NOSPLIT,$0
|
|
B ·Shutdown(SB)
|
|
|
|
TEXT ·Vectors(SB),NOSPLIT,$0
|
|
B ·El1_sync_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El1_irq_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El1_fiq_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El1_error_invalid(SB)
|
|
nop31Instructions()
|
|
|
|
B ·El1_sync(SB)
|
|
nop31Instructions()
|
|
B ·El1_irq(SB)
|
|
nop31Instructions()
|
|
B ·El1_fiq(SB)
|
|
nop31Instructions()
|
|
B ·El1_error(SB)
|
|
nop31Instructions()
|
|
|
|
B ·El0_sync(SB)
|
|
nop31Instructions()
|
|
B ·El0_irq(SB)
|
|
nop31Instructions()
|
|
B ·El0_fiq(SB)
|
|
nop31Instructions()
|
|
B ·El0_error(SB)
|
|
nop31Instructions()
|
|
|
|
B ·El0_sync_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El0_irq_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El0_fiq_invalid(SB)
|
|
nop31Instructions()
|
|
B ·El0_error_invalid(SB)
|
|
nop31Instructions()
|
|
|
|
WORD $0xd503201f //nop
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|
|
WORD $0xd503201f
|
|
nop31Instructions()
|