368 lines
11 KiB
C++
368 lines
11 KiB
C++
// Copyright 2018 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <signal.h>
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#include "gtest/gtest.h"
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#include "test/util/logging.h"
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#include "test/util/platform_util.h"
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#include "test/util/signal_util.h"
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#include "test/util/test_util.h"
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namespace gvisor {
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namespace testing {
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// Default value for the x87 FPU control word. See Intel SDM Vol 1, Ch 8.1.5
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// "x87 FPU Control Word".
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constexpr uint16_t kX87ControlWordDefault = 0x37f;
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// Mask for the divide-by-zero exception.
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constexpr uint16_t kX87ControlWordDiv0Mask = 1 << 2;
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// Default value for the SSE control register (MXCSR). See Intel SDM Vol 1, Ch
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// 11.6.4 "Initialization of SSE/SSE3 Extensions".
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constexpr uint32_t kMXCSRDefault = 0x1f80;
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// Mask for the divide-by-zero exception.
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constexpr uint32_t kMXCSRDiv0Mask = 1 << 9;
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// Flag for a pending divide-by-zero exception.
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constexpr uint32_t kMXCSRDiv0Flag = 1 << 2;
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void inline Halt() { asm("hlt\r\n"); }
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void inline SetAlignmentCheck() {
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asm("subq $128, %%rsp\r\n" // Avoid potential red zone clobber
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"pushf\r\n"
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"pop %%rax\r\n"
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"or $0x40000, %%rax\r\n"
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"push %%rax\r\n"
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"popf\r\n"
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"addq $128, %%rsp\r\n"
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:
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:
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: "ax");
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}
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void inline ClearAlignmentCheck() {
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asm("subq $128, %%rsp\r\n" // Avoid potential red zone clobber
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"pushf\r\n"
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"pop %%rax\r\n"
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"mov $0x40000, %%rbx\r\n"
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"not %%rbx\r\n"
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"and %%rbx, %%rax\r\n"
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"push %%rax\r\n"
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"popf\r\n"
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"addq $128, %%rsp\r\n"
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:
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:
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: "ax", "bx");
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}
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void inline Int3Normal() { asm(".byte 0xcd, 0x03\r\n"); }
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void inline Int3Compact() { asm(".byte 0xcc\r\n"); }
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void InIOHelper(int width, int value) {
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EXPECT_EXIT(
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{
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switch (width) {
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case 1:
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asm volatile("inb %%dx, %%al" ::"d"(value) : "%eax");
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break;
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case 2:
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asm volatile("inw %%dx, %%ax" ::"d"(value) : "%eax");
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break;
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case 4:
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asm volatile("inl %%dx, %%eax" ::"d"(value) : "%eax");
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break;
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default:
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FAIL() << "invalid input width, only 1, 2 or 4 is allowed";
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}
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},
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::testing::KilledBySignal(SIGSEGV), "");
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}
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TEST(ExceptionTest, Halt) {
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// In order to prevent the regular handler from messing with things (and
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// perhaps refaulting until some other signal occurs), we reset the handler to
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// the default action here and ensure that it dies correctly.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGSEGV, sa));
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EXPECT_EXIT(Halt(), ::testing::KilledBySignal(SIGSEGV), "");
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}
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TEST(ExceptionTest, DivideByZero) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGFPE, sa));
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EXPECT_EXIT(
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{
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uint32_t remainder;
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uint32_t quotient;
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uint32_t divisor = 0;
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uint64_t value = 1;
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asm("divl 0(%2)\r\n"
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: "=d"(remainder), "=a"(quotient)
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: "r"(&divisor), "d"(value >> 32), "a"(value));
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TEST_CHECK(quotient > 0); // Force dependency.
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},
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::testing::KilledBySignal(SIGFPE), "");
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}
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// By default, x87 exceptions are masked and simply return a default value.
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TEST(ExceptionTest, X87DivideByZeroMasked) {
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm("fildl %[value]\r\n"
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"fidivl %[divisor]\r\n"
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"fistpl %[quotient]\r\n"
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: [ quotient ] "=m"(quotient)
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: [ value ] "m"(value), [ divisor ] "m"(divisor));
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EXPECT_EQ(quotient, INT32_MIN);
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}
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// When unmasked, division by zero raises SIGFPE.
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TEST(ExceptionTest, X87DivideByZeroUnmasked) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGFPE, sa));
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EXPECT_EXIT(
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{
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// Clear the divide by zero exception mask.
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constexpr uint16_t kControlWord =
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kX87ControlWordDefault & ~kX87ControlWordDiv0Mask;
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm volatile(
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"fldcw %[cw]\r\n"
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"fildl %[value]\r\n"
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"fidivl %[divisor]\r\n"
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"fistpl %[quotient]\r\n"
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: [ quotient ] "=m"(quotient)
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: [ cw ] "m"(kControlWord), [ value ] "m"(value),
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[ divisor ] "m"(divisor));
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},
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::testing::KilledBySignal(SIGFPE), "");
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}
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// Pending exceptions in the x87 status register are not clobbered by syscalls.
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TEST(ExceptionTest, X87StatusClobber) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGFPE, sa));
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EXPECT_EXIT(
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{
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// Clear the divide by zero exception mask.
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constexpr uint16_t kControlWord =
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kX87ControlWordDefault & ~kX87ControlWordDiv0Mask;
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm volatile(
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"fildl %[value]\r\n"
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"fidivl %[divisor]\r\n"
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// Exception is masked, so it does not occur here.
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"fistpl %[quotient]\r\n"
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// SYS_getpid placed in rax by constraint.
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"syscall\r\n"
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// Unmask exception. The syscall didn't clobber the pending
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// exception, so now it can be raised.
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//
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// N.B. "a floating-point exception will be generated upon execution
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// of the *next* floating-point instruction".
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"fldcw %[cw]\r\n"
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"fwait\r\n"
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: [ quotient ] "=m"(quotient)
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: [ value ] "m"(value), [ divisor ] "m"(divisor), "a"(SYS_getpid),
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[ cw ] "m"(kControlWord)
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: "rcx", "r11");
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},
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::testing::KilledBySignal(SIGFPE), "");
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}
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// By default, SSE exceptions are masked and simply return a default value.
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TEST(ExceptionTest, SSEDivideByZeroMasked) {
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uint32_t status;
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm("cvtsi2ssl %[value], %%xmm0\r\n"
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"cvtsi2ssl %[divisor], %%xmm1\r\n"
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"divss %%xmm1, %%xmm0\r\n"
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"cvtss2sil %%xmm0, %[quotient]\r\n"
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: [ quotient ] "=r"(quotient), [ status ] "=r"(status)
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: [ value ] "r"(value), [ divisor ] "r"(divisor)
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: "xmm0", "xmm1");
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EXPECT_EQ(quotient, INT32_MIN);
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}
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// When unmasked, division by zero raises SIGFPE.
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TEST(ExceptionTest, SSEDivideByZeroUnmasked) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGFPE, sa));
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EXPECT_EXIT(
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{
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// Clear the divide by zero exception mask.
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constexpr uint32_t kMXCSR = kMXCSRDefault & ~kMXCSRDiv0Mask;
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm volatile(
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"ldmxcsr %[mxcsr]\r\n"
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"cvtsi2ssl %[value], %%xmm0\r\n"
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"cvtsi2ssl %[divisor], %%xmm1\r\n"
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"divss %%xmm1, %%xmm0\r\n"
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"cvtss2sil %%xmm0, %[quotient]\r\n"
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: [ quotient ] "=r"(quotient)
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: [ mxcsr ] "m"(kMXCSR), [ value ] "r"(value),
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[ divisor ] "r"(divisor)
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: "xmm0", "xmm1");
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},
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::testing::KilledBySignal(SIGFPE), "");
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}
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// Pending exceptions in the SSE status register are not clobbered by syscalls.
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TEST(ExceptionTest, SSEStatusClobber) {
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uint32_t mxcsr;
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int32_t quotient;
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int32_t value = 1;
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int32_t divisor = 0;
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asm("cvtsi2ssl %[value], %%xmm0\r\n"
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"cvtsi2ssl %[divisor], %%xmm1\r\n"
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"divss %%xmm1, %%xmm0\r\n"
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// Exception is masked, so it does not occur here.
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"cvtss2sil %%xmm0, %[quotient]\r\n"
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// SYS_getpid placed in rax by constraint.
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"syscall\r\n"
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// Intel SDM Vol 1, Ch 10.2.3.1 "SIMD Floating-Point Mask and Flag Bits":
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// "If LDMXCSR or FXRSTOR clears a mask bit and sets the corresponding
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// exception flag bit, a SIMD floating-point exception will not be
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// generated as a result of this change. The unmasked exception will be
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// generated only upon the execution of the next SSE/SSE2/SSE3 instruction
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// that detects the unmasked exception condition."
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//
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// Though ambiguous, empirical evidence indicates that this means that
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// exception flags set in the status register will never cause an
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// exception to be raised; only a new exception condition will do so.
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//
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// Thus here we just check for the flag itself rather than trying to raise
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// the exception.
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"stmxcsr %[mxcsr]\r\n"
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: [ quotient ] "=r"(quotient), [ mxcsr ] "+m"(mxcsr)
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: [ value ] "r"(value), [ divisor ] "r"(divisor), "a"(SYS_getpid)
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: "xmm0", "xmm1", "rcx", "r11");
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EXPECT_TRUE(mxcsr & kMXCSRDiv0Flag);
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}
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TEST(ExceptionTest, IOAccessFault) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGSEGV, sa));
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InIOHelper(1, 0x0);
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InIOHelper(2, 0x7);
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InIOHelper(4, 0x6);
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InIOHelper(1, 0xffff);
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InIOHelper(2, 0xffff);
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InIOHelper(4, 0xfffd);
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}
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TEST(ExceptionTest, Alignment) {
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SetAlignmentCheck();
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ClearAlignmentCheck();
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}
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TEST(ExceptionTest, AlignmentHalt) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGSEGV, sa));
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// Reported upstream. We need to ensure that bad flags are cleared even in
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// fault paths. Set the alignment flag and then generate an exception.
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EXPECT_EXIT(
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{
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SetAlignmentCheck();
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Halt();
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},
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::testing::KilledBySignal(SIGSEGV), "");
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}
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TEST(ExceptionTest, AlignmentCheck) {
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SKIP_IF(PlatformSupportAlignmentCheck() != PlatformSupport::Allowed);
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGBUS, sa));
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EXPECT_EXIT(
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{
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char array[16];
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SetAlignmentCheck();
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for (int i = 0; i < 8; i++) {
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// At least 7/8 offsets will be unaligned here.
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uint64_t* ptr = reinterpret_cast<uint64_t*>(&array[i]);
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asm("mov %0, 0(%0)\r\n" : : "r"(ptr) : "ax");
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}
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},
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::testing::KilledBySignal(SIGBUS), "");
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}
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TEST(ExceptionTest, Int3Normal) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGTRAP, sa));
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EXPECT_EXIT(Int3Normal(), ::testing::KilledBySignal(SIGTRAP), "");
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}
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TEST(ExceptionTest, Int3Compact) {
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// See above.
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struct sigaction sa = {};
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sa.sa_handler = SIG_DFL;
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auto const cleanup = ASSERT_NO_ERRNO_AND_VALUE(ScopedSigaction(SIGTRAP, sa));
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EXPECT_EXIT(Int3Compact(), ::testing::KilledBySignal(SIGTRAP), "");
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}
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} // namespace testing
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} // namespace gvisor
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