213 lines
4.2 KiB
ArmAsm
213 lines
4.2 KiB
ArmAsm
// Copyright 2018 The gVisor Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "funcdata.h"
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#include "textflag.h"
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// fxrstor loads floating point state.
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//
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// The code corresponds to:
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//
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// fxrstor64 (%rbx)
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//
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TEXT ·fxrstor(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), BX
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MOVL $0xffffffff, AX
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MOVL $0xffffffff, DX
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BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x0b;
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RET
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// xrstor loads floating point state.
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//
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// The code corresponds to:
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//
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// xrstor (%rdi)
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//
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TEXT ·xrstor(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), DI
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MOVL $0xffffffff, AX
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MOVL $0xffffffff, DX
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BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x2f;
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RET
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// fxsave saves floating point state.
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//
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// The code corresponds to:
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//
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// fxsave64 (%rbx)
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//
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TEXT ·fxsave(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), BX
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MOVL $0xffffffff, AX
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MOVL $0xffffffff, DX
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BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x03;
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RET
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// xsave saves floating point state.
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//
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// The code corresponds to:
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//
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// xsave (%rdi)
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//
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TEXT ·xsave(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), DI
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MOVL $0xffffffff, AX
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MOVL $0xffffffff, DX
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BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x27;
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RET
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// xsaveopt saves floating point state.
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//
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// The code corresponds to:
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//
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// xsaveopt (%rdi)
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//
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TEXT ·xsaveopt(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), DI
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MOVL $0xffffffff, AX
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MOVL $0xffffffff, DX
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BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0x37;
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RET
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// wrfsbase writes to the FS base.
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//
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// The code corresponds to:
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//
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// wrfsbase %rax
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//
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TEXT ·wrfsbase(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), AX
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BYTE $0xf3; BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0xd0;
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RET
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// wrfsmsr writes to the FSBASE MSR.
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//
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// The code corresponds to:
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//
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// wrmsr (writes EDX:EAX to the MSR in ECX)
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//
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TEXT ·wrfsmsr(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), AX
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MOVQ AX, DX
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SHRQ $32, DX
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MOVQ $0xc0000100, CX // MSR_FS_BASE
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BYTE $0x0f; BYTE $0x30;
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RET
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// wrgsbase writes to the GS base.
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//
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// The code corresponds to:
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//
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// wrgsbase %rax
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//
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TEXT ·wrgsbase(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), AX
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BYTE $0xf3; BYTE $0x48; BYTE $0x0f; BYTE $0xae; BYTE $0xd8;
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RET
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// wrgsmsr writes to the GSBASE MSR.
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//
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// See wrfsmsr.
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TEXT ·wrgsmsr(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), AX
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MOVQ AX, DX
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SHRQ $32, DX
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MOVQ $0xc0000101, CX // MSR_GS_BASE
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BYTE $0x0f; BYTE $0x30; // WRMSR
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RET
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// readCR2 reads the current CR2 value.
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//
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// The code corresponds to:
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//
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// mov %cr2, %rax
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//
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TEXT ·readCR2(SB),NOSPLIT,$0-8
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BYTE $0x0f; BYTE $0x20; BYTE $0xd0;
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MOVQ AX, ret+0(FP)
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RET
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// fninit initializes the floating point unit.
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//
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// The code corresponds to:
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//
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// fninit
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TEXT ·fninit(SB),NOSPLIT,$0
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BYTE $0xdb; BYTE $0xe3;
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RET
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// xsetbv writes to an extended control register.
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//
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// The code corresponds to:
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//
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// xsetbv
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//
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TEXT ·xsetbv(SB),NOSPLIT,$0-16
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MOVL reg+0(FP), CX
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MOVL value+8(FP), AX
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MOVL value+12(FP), DX
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BYTE $0x0f; BYTE $0x01; BYTE $0xd1;
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RET
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// xgetbv reads an extended control register.
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//
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// The code corresponds to:
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//
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// xgetbv
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//
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TEXT ·xgetbv(SB),NOSPLIT,$0-16
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MOVL reg+0(FP), CX
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BYTE $0x0f; BYTE $0x01; BYTE $0xd0;
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MOVL AX, ret+8(FP)
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MOVL DX, ret+12(FP)
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RET
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// wrmsr writes to a control register.
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//
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// The code corresponds to:
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//
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// wrmsr
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//
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TEXT ·wrmsr(SB),NOSPLIT,$0-16
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MOVL reg+0(FP), CX
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MOVL value+8(FP), AX
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MOVL value+12(FP), DX
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BYTE $0x0f; BYTE $0x30;
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RET
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// rdmsr reads a control register.
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//
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// The code corresponds to:
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//
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// rdmsr
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//
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TEXT ·rdmsr(SB),NOSPLIT,$0-16
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MOVL reg+0(FP), CX
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BYTE $0x0f; BYTE $0x32;
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MOVL AX, ret+8(FP)
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MOVL DX, ret+12(FP)
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RET
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// stmxcsr reads the MXCSR control and status register.
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TEXT ·stmxcsr(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), SI
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STMXCSR (SI)
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RET
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// ldmxcsr writes to the MXCSR control and status register.
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TEXT ·ldmxcsr(SB),NOSPLIT,$0-8
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MOVQ addr+0(FP), SI
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LDMXCSR (SI)
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RET
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