614 lines
20 KiB
Go
614 lines
20 KiB
Go
// Copyright 2018 Google Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// +build amd64 i386
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package arch
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import (
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"fmt"
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"io"
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"sync"
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"syscall"
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"gvisor.googlesource.com/gvisor/pkg/binary"
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"gvisor.googlesource.com/gvisor/pkg/cpuid"
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"gvisor.googlesource.com/gvisor/pkg/log"
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rpb "gvisor.googlesource.com/gvisor/pkg/sentry/arch/registers_go_proto"
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"gvisor.googlesource.com/gvisor/pkg/sentry/usermem"
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"gvisor.googlesource.com/gvisor/pkg/syserror"
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)
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// System-related constants for x86.
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const (
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// SyscallWidth is the width of syscall, sysenter, and int 80 insturctions.
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SyscallWidth = 2
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)
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// EFLAGS register bits.
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const (
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// eflagsCF is the mask for the carry flag.
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eflagsCF = uint64(1) << 0
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// eflagsPF is the mask for the parity flag.
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eflagsPF = uint64(1) << 2
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// eflagsAF is the mask for the auxiliary carry flag.
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eflagsAF = uint64(1) << 4
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// eflagsZF is the mask for the zero flag.
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eflagsZF = uint64(1) << 6
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// eflagsSF is the mask for the sign flag.
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eflagsSF = uint64(1) << 7
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// eflagsTF is the mask for the trap flag.
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eflagsTF = uint64(1) << 8
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// eflagsIF is the mask for the interrupt flag.
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eflagsIF = uint64(1) << 9
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// eflagsDF is the mask for the direction flag.
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eflagsDF = uint64(1) << 10
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// eflagsOF is the mask for the overflow flag.
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eflagsOF = uint64(1) << 11
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// eflagsIOPL is the mask for the I/O privilege level.
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eflagsIOPL = uint64(3) << 12
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// eflagsNT is the mask for the nested task bit.
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eflagsNT = uint64(1) << 14
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// eflagsRF is the mask for the resume flag.
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eflagsRF = uint64(1) << 16
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// eflagsVM is the mask for the virtual mode bit.
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eflagsVM = uint64(1) << 17
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// eflagsAC is the mask for the alignment check / access control bit.
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eflagsAC = uint64(1) << 18
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// eflagsVIF is the mask for the virtual interrupt flag.
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eflagsVIF = uint64(1) << 19
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// eflagsVIP is the mask for the virtual interrupt pending bit.
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eflagsVIP = uint64(1) << 20
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// eflagsID is the mask for the CPUID detection bit.
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eflagsID = uint64(1) << 21
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// eflagsPtraceMutable is the mask for the set of EFLAGS that may be
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// changed by ptrace(PTRACE_SETREGS). eflagsPtraceMutable is analogous to
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// Linux's FLAG_MASK.
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eflagsPtraceMutable = eflagsCF | eflagsPF | eflagsAF | eflagsZF | eflagsSF | eflagsTF | eflagsDF | eflagsOF | eflagsRF | eflagsAC | eflagsNT
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// eflagsRestorable is the mask for the set of EFLAGS that may be changed by
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// SignalReturn. eflagsRestorable is analogous to Linux's FIX_EFLAGS.
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eflagsRestorable = eflagsAC | eflagsOF | eflagsDF | eflagsTF | eflagsSF | eflagsZF | eflagsAF | eflagsPF | eflagsCF | eflagsRF
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)
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// Segment selectors. See arch/x86/include/asm/segment.h.
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const (
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userCS = 0x33 // guest ring 3 code selector
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user32CS = 0x23 // guest ring 3 32 bit code selector
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userDS = 0x2b // guest ring 3 data selector
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_FS_TLS_SEL = 0x63 // Linux FS thread-local storage selector
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_GS_TLS_SEL = 0x6b // Linux GS thread-local storage selector
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)
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var (
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// TrapInstruction is the x86 trap instruction.
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TrapInstruction = [1]byte{0xcc}
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// CPUIDInstruction is the x86 CPUID instruction.
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CPUIDInstruction = [2]byte{0xf, 0xa2}
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// X86TrapFlag is an exported const for use by other packages.
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X86TrapFlag uint64 = (1 << 8)
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)
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// x86FPState is x86 floating point state.
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type x86FPState []byte
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// initX86FPState (defined in asm files) sets up initial state.
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func initX86FPState(data *FloatingPointData, useXsave bool)
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func newX86FPStateSlice() []byte {
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size, align := cpuid.HostFeatureSet().ExtendedStateSize()
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capacity := size
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// Always use at least 4096 bytes.
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if capacity < 4096 {
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capacity = 4096
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}
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return alignedBytes(capacity, align)[:size]
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}
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// newX86FPState returns an initialized floating point state.
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//
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// The returned state is large enough to store all floating point state
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// supported by host, even if the app won't use much of it due to a restricted
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// FeatureSet. Since they may still be able to see state not advertised by
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// CPUID we must ensure it does not contain any sentry state.
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func newX86FPState() x86FPState {
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f := x86FPState(newX86FPStateSlice())
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initX86FPState(f.FloatingPointData(), cpuid.HostFeatureSet().UseXsave())
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return f
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}
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// fork creates and returns an identical copy of the x86 floating point state.
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func (f x86FPState) fork() x86FPState {
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n := x86FPState(newX86FPStateSlice())
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copy(n, f)
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return n
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}
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// FloatingPointData returns the raw data pointer.
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func (f x86FPState) FloatingPointData() *FloatingPointData {
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return (*FloatingPointData)(&f[0])
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}
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// NewFloatingPointData returns a new floating point data blob.
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//
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// This is primarily for use in tests.
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func NewFloatingPointData() *FloatingPointData {
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return (*FloatingPointData)(&(newX86FPState()[0]))
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}
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// State contains the common architecture bits for X86 (the build tag of this
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// file ensures it's only built on x86).
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type State struct {
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// The system registers.
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Regs syscall.PtraceRegs `state:".(syscallPtraceRegs)"`
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// Our floating point state.
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x86FPState `state:"wait"`
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// FeatureSet is a pointer to the currently active feature set.
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FeatureSet *cpuid.FeatureSet
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}
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// Proto returns a protobuf representation of the system registers in State.
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func (s State) Proto() *rpb.Registers {
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regs := &rpb.AMD64Registers{
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Rax: s.Regs.Rax,
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Rbx: s.Regs.Rbx,
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Rcx: s.Regs.Rcx,
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Rdx: s.Regs.Rdx,
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Rsi: s.Regs.Rsi,
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Rdi: s.Regs.Rdi,
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Rsp: s.Regs.Rsp,
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Rbp: s.Regs.Rbp,
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R8: s.Regs.R8,
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R9: s.Regs.R9,
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R10: s.Regs.R10,
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R11: s.Regs.R11,
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R12: s.Regs.R12,
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R13: s.Regs.R13,
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R14: s.Regs.R14,
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R15: s.Regs.R15,
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Rip: s.Regs.Rip,
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Rflags: s.Regs.Eflags,
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OrigRax: s.Regs.Orig_rax,
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Cs: s.Regs.Cs,
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Ds: s.Regs.Ds,
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Es: s.Regs.Es,
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Fs: s.Regs.Fs,
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Gs: s.Regs.Gs,
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Ss: s.Regs.Ss,
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FsBase: s.Regs.Fs_base,
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GsBase: s.Regs.Gs_base,
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}
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return &rpb.Registers{Arch: &rpb.Registers_Amd64{Amd64: regs}}
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}
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// Fork creates and returns an identical copy of the state.
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func (s *State) Fork() State {
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return State{
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Regs: s.Regs,
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x86FPState: s.x86FPState.fork(),
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FeatureSet: s.FeatureSet,
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}
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}
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// StateData implements Context.StateData.
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func (s *State) StateData() *State {
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return s
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}
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// CPUIDEmulate emulates a cpuid instruction.
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func (s *State) CPUIDEmulate(l log.Logger) {
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argax := uint32(s.Regs.Rax)
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argcx := uint32(s.Regs.Rcx)
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ax, bx, cx, dx := s.FeatureSet.EmulateID(argax, argcx)
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s.Regs.Rax = uint64(ax)
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s.Regs.Rbx = uint64(bx)
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s.Regs.Rcx = uint64(cx)
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s.Regs.Rdx = uint64(dx)
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l.Debugf("CPUID(%x,%x): %x %x %x %x", argax, argcx, ax, bx, cx, dx)
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}
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// SingleStep implements Context.SingleStep.
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func (s *State) SingleStep() bool {
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return s.Regs.Eflags&X86TrapFlag != 0
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}
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// SetSingleStep enables single stepping.
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func (s *State) SetSingleStep() {
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// Set the trap flag.
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s.Regs.Eflags |= X86TrapFlag
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}
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// ClearSingleStep enables single stepping.
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func (s *State) ClearSingleStep() {
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// Clear the trap flag.
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s.Regs.Eflags &= ^X86TrapFlag
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}
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// RegisterMap returns a map of all registers.
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func (s *State) RegisterMap() (map[string]uintptr, error) {
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return map[string]uintptr{
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"R15": uintptr(s.Regs.R15),
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"R14": uintptr(s.Regs.R14),
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"R13": uintptr(s.Regs.R13),
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"R12": uintptr(s.Regs.R12),
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"Rbp": uintptr(s.Regs.Rbp),
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"Rbx": uintptr(s.Regs.Rbx),
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"R11": uintptr(s.Regs.R11),
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"R10": uintptr(s.Regs.R10),
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"R9": uintptr(s.Regs.R9),
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"R8": uintptr(s.Regs.R8),
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"Rax": uintptr(s.Regs.Rax),
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"Rcx": uintptr(s.Regs.Rcx),
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"Rdx": uintptr(s.Regs.Rdx),
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"Rsi": uintptr(s.Regs.Rsi),
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"Rdi": uintptr(s.Regs.Rdi),
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"Orig_rax": uintptr(s.Regs.Orig_rax),
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"Rip": uintptr(s.Regs.Rip),
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"Cs": uintptr(s.Regs.Cs),
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"Eflags": uintptr(s.Regs.Eflags),
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"Rsp": uintptr(s.Regs.Rsp),
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"Ss": uintptr(s.Regs.Ss),
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"Fs_base": uintptr(s.Regs.Fs_base),
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"Gs_base": uintptr(s.Regs.Gs_base),
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"Ds": uintptr(s.Regs.Ds),
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"Es": uintptr(s.Regs.Es),
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"Fs": uintptr(s.Regs.Fs),
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"Gs": uintptr(s.Regs.Gs),
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}, nil
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}
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// PtraceGetRegs implements Context.PtraceGetRegs.
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func (s *State) PtraceGetRegs(dst io.Writer) (int, error) {
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return dst.Write(binary.Marshal(nil, usermem.ByteOrder, s.ptraceGetRegs()))
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}
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func (s *State) ptraceGetRegs() syscall.PtraceRegs {
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regs := s.Regs
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// These may not be initialized.
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if regs.Cs == 0 || regs.Ss == 0 || regs.Eflags == 0 {
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regs.Eflags = eflagsIF
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regs.Cs = userCS
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regs.Ss = userDS
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}
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// As an optimization, Linux <4.7 implements 32-bit fs_base/gs_base
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// addresses using reserved descriptors in the GDT instead of the MSRs,
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// with selector values FS_TLS_SEL and GS_TLS_SEL respectively. These
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// values are actually visible in struct user_regs_struct::fs/gs;
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// arch/x86/kernel/ptrace.c:getreg() doesn't attempt to sanitize struct
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// thread_struct::fsindex/gsindex.
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//
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// We always use fs == gs == 0 when fs_base/gs_base is in use, for
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// simplicity.
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//
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// Luckily, Linux <4.7 silently ignores setting fs/gs to 0 via
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// arch/x86/kernel/ptrace.c:set_segment_reg() when fs_base/gs_base is a
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// 32-bit value and fsindex/gsindex indicates that this optimization is
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// in use, as well as the reverse case of setting fs/gs to
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// FS/GS_TLS_SEL when fs_base/gs_base is a 64-bit value. (We do the
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// same in PtraceSetRegs.)
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//
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// TODO: Remove this fixup since newer Linux doesn't have
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// this behavior anymore.
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if regs.Fs == 0 && regs.Fs_base <= 0xffffffff {
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regs.Fs = _FS_TLS_SEL
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}
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if regs.Gs == 0 && regs.Gs_base <= 0xffffffff {
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regs.Gs = _GS_TLS_SEL
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}
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return regs
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}
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var ptraceRegsSize = int(binary.Size(syscall.PtraceRegs{}))
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// PtraceSetRegs implements Context.PtraceSetRegs.
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func (s *State) PtraceSetRegs(src io.Reader) (int, error) {
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var regs syscall.PtraceRegs
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buf := make([]byte, ptraceRegsSize)
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if _, err := io.ReadFull(src, buf); err != nil {
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return 0, err
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}
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binary.Unmarshal(buf, usermem.ByteOrder, ®s)
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// Truncate segment registers to 16 bits.
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regs.Cs = uint64(uint16(regs.Cs))
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regs.Ds = uint64(uint16(regs.Ds))
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regs.Es = uint64(uint16(regs.Es))
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regs.Fs = uint64(uint16(regs.Fs))
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regs.Gs = uint64(uint16(regs.Gs))
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regs.Ss = uint64(uint16(regs.Ss))
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// In Linux this validation is via arch/x86/kernel/ptrace.c:putreg().
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if !isUserSegmentSelector(regs.Cs) {
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return 0, syscall.EIO
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}
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if regs.Ds != 0 && !isUserSegmentSelector(regs.Ds) {
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return 0, syscall.EIO
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}
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if regs.Es != 0 && !isUserSegmentSelector(regs.Es) {
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return 0, syscall.EIO
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}
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if regs.Fs != 0 && !isUserSegmentSelector(regs.Fs) {
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return 0, syscall.EIO
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}
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if regs.Gs != 0 && !isUserSegmentSelector(regs.Gs) {
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return 0, syscall.EIO
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}
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if !isUserSegmentSelector(regs.Ss) {
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return 0, syscall.EIO
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}
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if regs.Fs_base >= uint64(maxAddr64) {
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return 0, syscall.EIO
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}
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if regs.Gs_base >= uint64(maxAddr64) {
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return 0, syscall.EIO
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}
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// CS and SS are validated, but changes to them are otherwise silently
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// ignored on amd64.
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regs.Cs = s.Regs.Cs
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regs.Ss = s.Regs.Ss
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// fs_base/gs_base changes reset fs/gs via do_arch_prctl() on Linux.
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if regs.Fs_base != s.Regs.Fs_base {
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regs.Fs = 0
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}
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if regs.Gs_base != s.Regs.Gs_base {
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regs.Gs = 0
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}
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// Ignore "stale" TLS segment selectors for FS and GS. See comment in
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// ptraceGetRegs.
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if regs.Fs == _FS_TLS_SEL && regs.Fs_base != 0 {
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regs.Fs = 0
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}
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if regs.Gs == _GS_TLS_SEL && regs.Gs_base != 0 {
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regs.Gs = 0
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}
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regs.Eflags = (s.Regs.Eflags &^ eflagsPtraceMutable) | (regs.Eflags & eflagsPtraceMutable)
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s.Regs = regs
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return ptraceRegsSize, nil
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}
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// isUserSegmentSelector returns true if the given segment selector specifies a
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// privilege level of 3 (USER_RPL).
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func isUserSegmentSelector(reg uint64) bool {
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return reg&3 == 3
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}
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// ptraceFPRegsSize is the size in bytes of Linux's user_i387_struct, the type
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// manipulated by PTRACE_GETFPREGS and PTRACE_SETFPREGS on x86. Equivalently,
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// ptraceFPRegsSize is the size in bytes of the x86 FXSAVE area.
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const ptraceFPRegsSize = 512
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// PtraceGetFPRegs implements Context.PtraceGetFPRegs.
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func (s *State) PtraceGetFPRegs(dst io.Writer) (int, error) {
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return dst.Write(s.x86FPState[:ptraceFPRegsSize])
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}
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// PtraceSetFPRegs implements Context.PtraceSetFPRegs.
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func (s *State) PtraceSetFPRegs(src io.Reader) (int, error) {
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var f [ptraceFPRegsSize]byte
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n, err := io.ReadFull(src, f[:])
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if err != nil {
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return 0, err
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}
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// Force reserved bits in MXCSR to 0. This is consistent with Linux.
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sanitizeMXCSR(x86FPState(f[:]))
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// N.B. this only copies the beginning of the FP state, which
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// corresponds to the FXSAVE area.
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copy(s.x86FPState, f[:])
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return n, nil
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}
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const (
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// mxcsrOffset is the offset in bytes of the MXCSR field from the start of
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// the FXSAVE area. (Intel SDM Vol. 1, Table 10-2 "Format of an FXSAVE
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// Area")
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mxcsrOffset = 24
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// mxcsrMaskOffset is the offset in bytes of the MXCSR_MASK field from the
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// start of the FXSAVE area.
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mxcsrMaskOffset = 28
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)
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var (
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mxcsrMask uint32
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initMXCSRMask sync.Once
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)
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// sanitizeMXCSR coerces reserved bits in the MXCSR field of f to 0. ("FXRSTOR
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// generates a general-protection fault (#GP) in response to an attempt to set
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// any of the reserved bits of the MXCSR register." - Intel SDM Vol. 1, Section
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// 10.5.1.2 "SSE State")
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func sanitizeMXCSR(f x86FPState) {
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mxcsr := usermem.ByteOrder.Uint32(f[mxcsrOffset:])
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initMXCSRMask.Do(func() {
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temp := x86FPState(alignedBytes(uint(ptraceFPRegsSize), 16))
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initX86FPState(temp.FloatingPointData(), false /* useXsave */)
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mxcsrMask = usermem.ByteOrder.Uint32(temp[mxcsrMaskOffset:])
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if mxcsrMask == 0 {
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// "If the value of the MXCSR_MASK field is 00000000H, then the
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// MXCSR_MASK value is the default value of 0000FFBFH." - Intel SDM
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// Vol. 1, Section 11.6.6 "Guidelines for Writing to the MXCSR
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// Register"
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mxcsrMask = 0xffbf
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}
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})
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mxcsr &= mxcsrMask
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|
usermem.ByteOrder.PutUint32(f[mxcsrOffset:], mxcsr)
|
|
}
|
|
|
|
const (
|
|
// minXstateBytes is the minimum size in bytes of an x86 XSAVE area, equal
|
|
// to the size of the XSAVE legacy area (512 bytes) plus the size of the
|
|
// XSAVE header (64 bytes). Equivalently, minXstateBytes is GDB's
|
|
// X86_XSTATE_SSE_SIZE.
|
|
minXstateBytes = 512 + 64
|
|
|
|
// userXstateXCR0Offset is the offset in bytes of the USER_XSTATE_XCR0_WORD
|
|
// field in Linux's struct user_xstateregs, which is the type manipulated
|
|
// by ptrace(PTRACE_GET/SETREGSET, NT_X86_XSTATE). Equivalently,
|
|
// userXstateXCR0Offset is GDB's I386_LINUX_XSAVE_XCR0_OFFSET.
|
|
userXstateXCR0Offset = 464
|
|
|
|
// xstateBVOffset is the offset in bytes of the XSTATE_BV field in an x86
|
|
// XSAVE area.
|
|
xstateBVOffset = 512
|
|
|
|
// xsaveHeaderZeroedOffset and xsaveHeaderZeroedBytes indicate parts of the
|
|
// XSAVE header that we coerce to zero: "Bytes 15:8 of the XSAVE header is
|
|
// a state-component bitmap called XCOMP_BV. ... Bytes 63:16 of the XSAVE
|
|
// header are reserved." - Intel SDM Vol. 1, Section 13.4.2 "XSAVE Header".
|
|
// Linux ignores XCOMP_BV, but it's able to recover from XRSTOR #GP
|
|
// exceptions resulting from invalid values; we aren't. Linux also never
|
|
// uses the compacted format when doing XSAVE and doesn't even define the
|
|
// compaction extensions to XSAVE as a CPU feature, so for simplicity we
|
|
// assume no one is using them.
|
|
xsaveHeaderZeroedOffset = 512 + 8
|
|
xsaveHeaderZeroedBytes = 64 - 8
|
|
)
|
|
|
|
func (s *State) ptraceGetXstateRegs(dst io.Writer, maxlen int) (int, error) {
|
|
// N.B. s.x86FPState may contain more state than the application
|
|
// expects. We only copy the subset that would be in their XSAVE area.
|
|
ess, _ := s.FeatureSet.ExtendedStateSize()
|
|
f := make([]byte, ess)
|
|
copy(f, s.x86FPState)
|
|
// "The XSAVE feature set does not use bytes 511:416; bytes 463:416 are
|
|
// reserved." - Intel SDM Vol 1., Section 13.4.1 "Legacy Region of an XSAVE
|
|
// Area". Linux uses the first 8 bytes of this area to store the OS XSTATE
|
|
// mask. GDB relies on this: see
|
|
// gdb/x86-linux-nat.c:x86_linux_read_description().
|
|
usermem.ByteOrder.PutUint64(f[userXstateXCR0Offset:], s.FeatureSet.ValidXCR0Mask())
|
|
if len(f) > maxlen {
|
|
f = f[:maxlen]
|
|
}
|
|
return dst.Write(f)
|
|
}
|
|
|
|
func (s *State) ptraceSetXstateRegs(src io.Reader, maxlen int) (int, error) {
|
|
// Allow users to pass an xstate register set smaller than ours (they can
|
|
// mask bits out of XSTATE_BV), as long as it's at least minXstateBytes.
|
|
// Also allow users to pass a register set larger than ours; anything after
|
|
// their ExtendedStateSize will be ignored. (I think Linux technically
|
|
// permits setting a register set smaller than minXstateBytes, but it has
|
|
// the same silent truncation behavior in kernel/ptrace.c:ptrace_regset().)
|
|
if maxlen < minXstateBytes {
|
|
return 0, syscall.EFAULT
|
|
}
|
|
ess, _ := s.FeatureSet.ExtendedStateSize()
|
|
if maxlen > int(ess) {
|
|
maxlen = int(ess)
|
|
}
|
|
f := make([]byte, maxlen)
|
|
if _, err := io.ReadFull(src, f); err != nil {
|
|
return 0, err
|
|
}
|
|
// Force reserved bits in MXCSR to 0. This is consistent with Linux.
|
|
sanitizeMXCSR(x86FPState(f))
|
|
// Users can't enable *more* XCR0 bits than what we, and the CPU, support.
|
|
xstateBV := usermem.ByteOrder.Uint64(f[xstateBVOffset:])
|
|
xstateBV &= s.FeatureSet.ValidXCR0Mask()
|
|
usermem.ByteOrder.PutUint64(f[xstateBVOffset:], xstateBV)
|
|
// Force XCOMP_BV and reserved bytes in the XSAVE header to 0.
|
|
reserved := f[xsaveHeaderZeroedOffset : xsaveHeaderZeroedOffset+xsaveHeaderZeroedBytes]
|
|
for i := range reserved {
|
|
reserved[i] = 0
|
|
}
|
|
return copy(s.x86FPState, f), nil
|
|
}
|
|
|
|
// Register sets defined in include/uapi/linux/elf.h.
|
|
const (
|
|
_NT_PRSTATUS = 1
|
|
_NT_PRFPREG = 2
|
|
_NT_X86_XSTATE = 0x202
|
|
)
|
|
|
|
// PtraceGetRegSet implements Context.PtraceGetRegSet.
|
|
func (s *State) PtraceGetRegSet(regset uintptr, dst io.Writer, maxlen int) (int, error) {
|
|
switch regset {
|
|
case _NT_PRSTATUS:
|
|
if maxlen < ptraceRegsSize {
|
|
return 0, syserror.EFAULT
|
|
}
|
|
return s.PtraceGetRegs(dst)
|
|
case _NT_PRFPREG:
|
|
if maxlen < ptraceFPRegsSize {
|
|
return 0, syserror.EFAULT
|
|
}
|
|
return s.PtraceGetFPRegs(dst)
|
|
case _NT_X86_XSTATE:
|
|
return s.ptraceGetXstateRegs(dst, maxlen)
|
|
default:
|
|
return 0, syserror.EINVAL
|
|
}
|
|
}
|
|
|
|
// PtraceSetRegSet implements Context.PtraceSetRegSet.
|
|
func (s *State) PtraceSetRegSet(regset uintptr, src io.Reader, maxlen int) (int, error) {
|
|
switch regset {
|
|
case _NT_PRSTATUS:
|
|
if maxlen < ptraceRegsSize {
|
|
return 0, syserror.EFAULT
|
|
}
|
|
return s.PtraceSetRegs(src)
|
|
case _NT_PRFPREG:
|
|
if maxlen < ptraceFPRegsSize {
|
|
return 0, syserror.EFAULT
|
|
}
|
|
return s.PtraceSetFPRegs(src)
|
|
case _NT_X86_XSTATE:
|
|
return s.ptraceSetXstateRegs(src, maxlen)
|
|
default:
|
|
return 0, syserror.EINVAL
|
|
}
|
|
}
|
|
|
|
// FullRestore indicates whether a full restore is required.
|
|
func (s *State) FullRestore() bool {
|
|
// A fast system call return is possible only if
|
|
//
|
|
// * RCX matches the instruction pointer.
|
|
// * R11 matches our flags value.
|
|
// * Usermode does not expect to set either the resume flag or the
|
|
// virtual mode flags (unlikely.)
|
|
// * CS and SS are set to the standard selectors.
|
|
//
|
|
// That is, SYSRET results in the correct final state.
|
|
fastRestore := s.Regs.Rcx == s.Regs.Rip &&
|
|
s.Regs.Eflags == s.Regs.R11 &&
|
|
(s.Regs.Eflags&eflagsRF == 0) &&
|
|
(s.Regs.Eflags&eflagsVM == 0) &&
|
|
s.Regs.Cs == userCS &&
|
|
s.Regs.Ss == userDS
|
|
return !fastRestore
|
|
}
|
|
|
|
// New returns a new architecture context.
|
|
func New(arch Arch, fs *cpuid.FeatureSet) Context {
|
|
switch arch {
|
|
case AMD64:
|
|
return &context64{
|
|
State{
|
|
x86FPState: newX86FPState(),
|
|
FeatureSet: fs,
|
|
},
|
|
[]x86FPState(nil),
|
|
}
|
|
}
|
|
panic(fmt.Sprintf("unknown architecture %v", arch))
|
|
}
|